From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37347) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1akjVr-00033s-8L for qemu-devel@nongnu.org; Mon, 28 Mar 2016 22:36:12 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1akjVm-0006c1-QI for qemu-devel@nongnu.org; Mon, 28 Mar 2016 22:36:11 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:22011) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1akjVm-0006bF-Kp for qemu-devel@nongnu.org; Mon, 28 Mar 2016 22:36:06 -0400 From: Yongbok Kim Date: Mon, 28 Mar 2016 19:35:49 -0700 Message-ID: <1459218952-9408-1-git-send-email-yongbok.kim@imgtec.com> MIME-Version: 1.0 Content-Type: text/plain Subject: [Qemu-devel] [PATCH v3 0/3] mips: add Global Interrupt Controller List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Yongbok Kim , peter.maydell@linaro.org, crosthwaitepeter@gmail.com, leon.alrae@imgtec.com, aurelien@aurel32.net This patchset implement MIPS Global Interrupt Controller. The Global Interrupt Controller (GIC) is responsible for mapping each internal and external interrupt to the correct location for servicing. Limitation: Level triggering only GIC CounterHi not implemented (Countbits = 32bits) DINT not implemented Local WatchDog, Fast Debug Channel, Perf Counter not implemented It is based on the earlier un-merged GIC implementation. https://lists.gnu.org/archive/html/qemu-devel/2013-03/msg00194.html For more information, http://imgtec.com/mips/warrior/p-class-p5600-multiprocessor-core/ http://imgtec.com/mips/warrior/i-class-i6400-multiprocessor-core/ v3: * rebased to top of CPS changes * removed GCR from the patchset as CPS patchset includes it * added checking boundaries * fixed racy code (James) * split gic interval timer into separate file hw/timer/mips_gictimer.c * updated review comments (James, Leon) * cosmetic changes v2: * added user mode section (James) * moved mips_gic.c into hw/intc, mips_gcr.c into hw/misc (PeterM, PeterC) * renamed obvious duplications (Leon) * renamed gic_irqs into irq_state (Leon) * removed pointer to gic IRQs from env (Leon) * fixed loading target_ulong CMGCRBase (Leon) * removed unimplemented registers (Leon) * fixed writing to wedge register (Leon) * removed magic numbers * updated usage of map_vp to indicate not mapped * cosmetic changes and other review comments Leon Alrae (1): hw/mips/cps: create GIC block inside CPS Yongbok Kim (2): hw/mips: implement GIC Interval Timer hw/mips: implement Global Interrupt Controller hw/intc/Makefile.objs | 1 + hw/intc/mips_gic.c | 459 ++++++++++++++++++++++++++++++++++++++ hw/mips/cps.c | 25 ++- hw/mips/mips_malta.c | 4 +- hw/misc/mips_cmgcr.c | 33 +++ hw/timer/Makefile.objs | 1 + hw/timer/mips_gictimer.c | 141 ++++++++++++ include/hw/intc/mips_gic.h | 215 ++++++++++++++++++ include/hw/mips/cps.h | 2 + include/hw/misc/mips_cmgcr.h | 9 + include/hw/timer/mips_gictimer.h | 46 ++++ 11 files changed, 926 insertions(+), 10 deletions(-) create mode 100644 hw/intc/mips_gic.c create mode 100644 hw/timer/mips_gictimer.c create mode 100644 include/hw/intc/mips_gic.h create mode 100644 include/hw/timer/mips_gictimer.h