From: Leon Alrae <leon.alrae@imgtec.com>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL v2 09/21] hw/mips_malta: move CPU creation to a separate function
Date: Wed, 30 Mar 2016 09:49:50 +0100 [thread overview]
Message-ID: <1459327802-5102-10-git-send-email-leon.alrae@imgtec.com> (raw)
In-Reply-To: <1459327802-5102-1-git-send-email-leon.alrae@imgtec.com>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
---
hw/mips/mips_malta.c | 68 ++++++++++++++++++++++++++++++----------------------
1 file changed, 39 insertions(+), 29 deletions(-)
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index 60e8a8d..cc32a44 100644
--- a/hw/mips/mips_malta.c
+++ b/hw/mips/mips_malta.c
@@ -908,12 +908,45 @@ static void main_cpu_reset(void *opaque)
}
}
+static void create_cpu(const char *cpu_model,
+ qemu_irq *cbus_irq, qemu_irq *i8259_irq)
+{
+ CPUMIPSState *env;
+ MIPSCPU *cpu;
+ int i;
+ if (cpu_model == NULL) {
+#ifdef TARGET_MIPS64
+ cpu_model = "20Kc";
+#else
+ cpu_model = "24Kf";
+#endif
+ }
+
+ for (i = 0; i < smp_cpus; i++) {
+ cpu = cpu_mips_init(cpu_model);
+ if (cpu == NULL) {
+ fprintf(stderr, "Unable to find CPU definition\n");
+ exit(1);
+ }
+ env = &cpu->env;
+
+ /* Init internal devices */
+ cpu_mips_irq_init_cpu(env);
+ cpu_mips_clock_init(env);
+ qemu_register_reset(main_cpu_reset, cpu);
+ }
+
+ cpu = MIPS_CPU(first_cpu);
+ env = &cpu->env;
+ *i8259_irq = env->irq[2];
+ *cbus_irq = env->irq[4];
+}
+
static
void mips_malta_init(MachineState *machine)
{
ram_addr_t ram_size = machine->ram_size;
ram_addr_t ram_low_size;
- const char *cpu_model = machine->cpu_model;
const char *kernel_filename = machine->kernel_filename;
const char *kernel_cmdline = machine->kernel_cmdline;
const char *initrd_filename = machine->initrd_filename;
@@ -930,9 +963,8 @@ void mips_malta_init(MachineState *machine)
int64_t kernel_entry, bootloader_run_addr;
PCIBus *pci_bus;
ISABus *isa_bus;
- MIPSCPU *cpu;
- CPUMIPSState *env;
qemu_irq *isa_irq;
+ qemu_irq cbus_irq, i8259_irq;
int piix4_devfn;
I2CBus *smbus;
int i;
@@ -962,30 +994,8 @@ void mips_malta_init(MachineState *machine)
}
}
- /* init CPUs */
- if (cpu_model == NULL) {
-#ifdef TARGET_MIPS64
- cpu_model = "20Kc";
-#else
- cpu_model = "24Kf";
-#endif
- }
-
- for (i = 0; i < smp_cpus; i++) {
- cpu = cpu_mips_init(cpu_model);
- if (cpu == NULL) {
- fprintf(stderr, "Unable to find CPU definition\n");
- exit(1);
- }
- env = &cpu->env;
-
- /* Init internal devices */
- cpu_mips_irq_init_cpu(env);
- cpu_mips_clock_init(env);
- qemu_register_reset(main_cpu_reset, cpu);
- }
- cpu = MIPS_CPU(first_cpu);
- env = &cpu->env;
+ /* create CPUs */
+ create_cpu(machine->cpu_model, &cbus_irq, &i8259_irq);
/* allocate RAM */
if (ram_size > (2048u << 20)) {
@@ -1026,7 +1036,7 @@ void mips_malta_init(MachineState *machine)
#endif
/* FPGA */
/* The CBUS UART is attached to the MIPS CPU INT2 pin, ie interrupt 4 */
- malta_fpga_init(system_memory, FPGA_ADDRESS, env->irq[4], serial_hds[2]);
+ malta_fpga_init(system_memory, FPGA_ADDRESS, cbus_irq, serial_hds[2]);
/* Load firmware in flash / BIOS. */
dinfo = drive_get(IF_PFLASH, 0, fl_idx);
@@ -1154,7 +1164,7 @@ void mips_malta_init(MachineState *machine)
/* Interrupt controller */
/* The 8259 is attached to the MIPS CPU INT0 pin, ie interrupt 2 */
- s->i8259 = i8259_init(isa_bus, env->irq[2]);
+ s->i8259 = i8259_init(isa_bus, i8259_irq);
isa_bus_irqs(isa_bus, s->i8259);
pci_piix4_ide_init(pci_bus, hd, piix4_devfn + 1);
--
2.1.0
next prev parent reply other threads:[~2016-03-30 8:50 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-03-30 8:49 [Qemu-devel] [PULL v2 00/21] target-mips queue for 2.6 Leon Alrae
2016-03-30 8:49 ` [Qemu-devel] [PULL v2 01/21] hw/mips: implement generic MIPS Coherent Processing System container Leon Alrae
2016-03-30 8:49 ` [Qemu-devel] [PULL v2 02/21] target-mips: add CMGCRBase register Leon Alrae
2016-03-30 8:49 ` [Qemu-devel] [PULL v2 03/21] hw/mips: add initial Global Config Register support Leon Alrae
2016-03-30 8:49 ` [Qemu-devel] [PULL v2 04/21] hw/mips/cps: create GCR block inside CPS Leon Alrae
2016-03-30 8:49 ` [Qemu-devel] [PULL v2 05/21] hw/mips: add initial Cluster Power Controller support Leon Alrae
2016-03-30 8:49 ` [Qemu-devel] [PULL v2 06/21] hw/mips/cps: create CPC block inside CPS Leon Alrae
2016-03-30 8:49 ` [Qemu-devel] [PULL v2 07/21] hw/mips_malta: remove CPUMIPSState from the write_bootloader() Leon Alrae
2016-03-30 8:49 ` [Qemu-devel] [PULL v2 08/21] hw/mips_malta: remove redundant irq and clock init Leon Alrae
2016-03-30 8:49 ` Leon Alrae [this message]
2016-03-30 8:49 ` [Qemu-devel] [PULL v2 10/21] hw/mips_malta: add CPS to Malta board Leon Alrae
2016-03-30 8:49 ` [Qemu-devel] [PULL v2 11/21] target-mips: enable CM GCR in MIPS64R6-generic CPU Leon Alrae
2016-03-30 8:49 ` [Qemu-devel] [PULL v2 12/21] hw/mips: implement ITC Configuration Tags and Storage Cells Leon Alrae
2016-03-30 8:49 ` [Qemu-devel] [PULL v2 13/21] hw/mips: implement ITC Storage - Control View Leon Alrae
2016-03-30 8:49 ` [Qemu-devel] [PULL v2 14/21] hw/mips: implement ITC Storage - Empty/Full Sync and Try Views Leon Alrae
2016-03-30 8:49 ` [Qemu-devel] [PULL v2 15/21] hw/mips: implement ITC Storage - P/V " Leon Alrae
2016-03-30 8:49 ` [Qemu-devel] [PULL v2 16/21] hw/mips: implement ITC Storage - Bypass View Leon Alrae
2016-03-30 8:49 ` [Qemu-devel] [PULL v2 17/21] target-mips: check CP0 enabled for CACHE instruction also in R6 Leon Alrae
2016-03-30 8:49 ` [Qemu-devel] [PULL v2 18/21] target-mips: make ITC Configuration Tags accessible to the CPU Leon Alrae
2016-03-30 8:50 ` [Qemu-devel] [PULL v2 19/21] hw/mips/cps: enable ITU for multithreading processors Leon Alrae
2016-03-30 8:50 ` [Qemu-devel] [PULL v2 20/21] target-mips: use CP0_CHECK for gen_m{f|t}hc0 Leon Alrae
2016-03-30 8:50 ` [Qemu-devel] [PULL v2 21/21] target-mips: add MAAR, MAARI register Leon Alrae
2016-03-30 16:12 ` [Qemu-devel] [PULL v2 00/21] target-mips queue for 2.6 Peter Maydell
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