From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34244) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1alBps-0002si-LK for qemu-devel@nongnu.org; Wed, 30 Mar 2016 04:50:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1alBpm-0001q1-To for qemu-devel@nongnu.org; Wed, 30 Mar 2016 04:50:44 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:43541) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1alBpm-0001pj-M1 for qemu-devel@nongnu.org; Wed, 30 Mar 2016 04:50:38 -0400 Received: from hhmail02.hh.imgtec.org (unknown [10.100.10.20]) by Websense Email Security Gateway with ESMTPS id 2FE675D6AB664 for ; Wed, 30 Mar 2016 09:50:36 +0100 (IST) From: Leon Alrae Date: Wed, 30 Mar 2016 09:49:52 +0100 Message-ID: <1459327802-5102-12-git-send-email-leon.alrae@imgtec.com> In-Reply-To: <1459327802-5102-1-git-send-email-leon.alrae@imgtec.com> References: <1459327802-5102-1-git-send-email-leon.alrae@imgtec.com> MIME-Version: 1.0 Content-Type: text/plain Subject: [Qemu-devel] [PULL v2 11/21] target-mips: enable CM GCR in MIPS64R6-generic CPU List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Indicate that in the MIPS64R6-generic CPU the memory-mapped Global Configuration Register Space is implemented. Signed-off-by: Leon Alrae --- target-mips/translate_init.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c index 3192db0..b44df9e 100644 --- a/target-mips/translate_init.c +++ b/target-mips/translate_init.c @@ -663,7 +663,8 @@ static const mips_def_t mips_defs[] = (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) | (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), .CP0_Config2 = MIPS_CONFIG2, - .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_MSAP) | + .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | + (1 << CP0C3_CMGCR) | (1 << CP0C3_MSAP) | (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) | (1 << CP0C3_RXI) | (1 << CP0C3_LPA), .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) | -- 2.1.0