From: Leon Alrae <leon.alrae@imgtec.com>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL v2 17/21] target-mips: check CP0 enabled for CACHE instruction also in R6
Date: Wed, 30 Mar 2016 09:49:58 +0100 [thread overview]
Message-ID: <1459327802-5102-18-git-send-email-leon.alrae@imgtec.com> (raw)
In-Reply-To: <1459327802-5102-1-git-send-email-leon.alrae@imgtec.com>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
---
target-mips/translate.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index a5b8805..65f2caf 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -17194,6 +17194,7 @@ static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx)
/* Treat as NOP. */
break;
case R6_OPC_CACHE:
+ check_cp0_enabled(ctx);
/* Treat as NOP. */
break;
case R6_OPC_SC:
--
2.1.0
next prev parent reply other threads:[~2016-03-30 8:50 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-03-30 8:49 [Qemu-devel] [PULL v2 00/21] target-mips queue for 2.6 Leon Alrae
2016-03-30 8:49 ` [Qemu-devel] [PULL v2 01/21] hw/mips: implement generic MIPS Coherent Processing System container Leon Alrae
2016-03-30 8:49 ` [Qemu-devel] [PULL v2 02/21] target-mips: add CMGCRBase register Leon Alrae
2016-03-30 8:49 ` [Qemu-devel] [PULL v2 03/21] hw/mips: add initial Global Config Register support Leon Alrae
2016-03-30 8:49 ` [Qemu-devel] [PULL v2 04/21] hw/mips/cps: create GCR block inside CPS Leon Alrae
2016-03-30 8:49 ` [Qemu-devel] [PULL v2 05/21] hw/mips: add initial Cluster Power Controller support Leon Alrae
2016-03-30 8:49 ` [Qemu-devel] [PULL v2 06/21] hw/mips/cps: create CPC block inside CPS Leon Alrae
2016-03-30 8:49 ` [Qemu-devel] [PULL v2 07/21] hw/mips_malta: remove CPUMIPSState from the write_bootloader() Leon Alrae
2016-03-30 8:49 ` [Qemu-devel] [PULL v2 08/21] hw/mips_malta: remove redundant irq and clock init Leon Alrae
2016-03-30 8:49 ` [Qemu-devel] [PULL v2 09/21] hw/mips_malta: move CPU creation to a separate function Leon Alrae
2016-03-30 8:49 ` [Qemu-devel] [PULL v2 10/21] hw/mips_malta: add CPS to Malta board Leon Alrae
2016-03-30 8:49 ` [Qemu-devel] [PULL v2 11/21] target-mips: enable CM GCR in MIPS64R6-generic CPU Leon Alrae
2016-03-30 8:49 ` [Qemu-devel] [PULL v2 12/21] hw/mips: implement ITC Configuration Tags and Storage Cells Leon Alrae
2016-03-30 8:49 ` [Qemu-devel] [PULL v2 13/21] hw/mips: implement ITC Storage - Control View Leon Alrae
2016-03-30 8:49 ` [Qemu-devel] [PULL v2 14/21] hw/mips: implement ITC Storage - Empty/Full Sync and Try Views Leon Alrae
2016-03-30 8:49 ` [Qemu-devel] [PULL v2 15/21] hw/mips: implement ITC Storage - P/V " Leon Alrae
2016-03-30 8:49 ` [Qemu-devel] [PULL v2 16/21] hw/mips: implement ITC Storage - Bypass View Leon Alrae
2016-03-30 8:49 ` Leon Alrae [this message]
2016-03-30 8:49 ` [Qemu-devel] [PULL v2 18/21] target-mips: make ITC Configuration Tags accessible to the CPU Leon Alrae
2016-03-30 8:50 ` [Qemu-devel] [PULL v2 19/21] hw/mips/cps: enable ITU for multithreading processors Leon Alrae
2016-03-30 8:50 ` [Qemu-devel] [PULL v2 20/21] target-mips: use CP0_CHECK for gen_m{f|t}hc0 Leon Alrae
2016-03-30 8:50 ` [Qemu-devel] [PULL v2 21/21] target-mips: add MAAR, MAARI register Leon Alrae
2016-03-30 16:12 ` [Qemu-devel] [PULL v2 00/21] target-mips queue for 2.6 Peter Maydell
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