From: Leon Alrae <leon.alrae@imgtec.com>
To: qemu-devel@nongnu.org
Cc: Yongbok Kim <yongbok.kim@imgtec.com>
Subject: [Qemu-devel] [PULL v2 20/21] target-mips: use CP0_CHECK for gen_m{f|t}hc0
Date: Wed, 30 Mar 2016 09:50:01 +0100 [thread overview]
Message-ID: <1459327802-5102-21-git-send-email-leon.alrae@imgtec.com> (raw)
In-Reply-To: <1459327802-5102-1-git-send-email-leon.alrae@imgtec.com>
From: Yongbok Kim <yongbok.kim@imgtec.com>
Reuse CP0_CHECK macro for gen_m{f|t}hc0.
Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
---
target-mips/translate.c | 46 +++++++++++++++++++++-------------------------
1 file changed, 21 insertions(+), 25 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 592e4e3..9bf7dfb 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -4775,13 +4775,18 @@ static inline void gen_mtc0_store32 (TCGv arg, target_ulong off)
tcg_temp_free_i32(t0);
}
+#define CP0_CHECK(c) \
+ do { \
+ if (!(c)) { \
+ goto cp0_unimplemented; \
+ } \
+ } while (0)
+
static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel)
{
const char *rn = "invalid";
- if (!(ctx->hflags & MIPS_HFLAG_ELPA)) {
- goto mfhc0_read_zero;
- }
+ CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
switch (reg) {
case 2:
@@ -4791,7 +4796,7 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel)
rn = "EntryLo0";
break;
default:
- goto mfhc0_read_zero;
+ goto cp0_unimplemented;
}
break;
case 3:
@@ -4801,7 +4806,7 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel)
rn = "EntryLo1";
break;
default:
- goto mfhc0_read_zero;
+ goto cp0_unimplemented;
}
break;
case 17:
@@ -4812,7 +4817,7 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel)
rn = "LLAddr";
break;
default:
- goto mfhc0_read_zero;
+ goto cp0_unimplemented;
}
break;
case 28:
@@ -4825,18 +4830,18 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel)
rn = "TagLo";
break;
default:
- goto mfhc0_read_zero;
+ goto cp0_unimplemented;
}
break;
default:
- goto mfhc0_read_zero;
+ goto cp0_unimplemented;
}
(void)rn; /* avoid a compiler warning */
LOG_DISAS("mfhc0 %s (reg %d sel %d)\n", rn, reg, sel);
return;
-mfhc0_read_zero:
+cp0_unimplemented:
LOG_DISAS("mfhc0 %s (reg %d sel %d)\n", rn, reg, sel);
tcg_gen_movi_tl(arg, 0);
}
@@ -4846,9 +4851,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel)
const char *rn = "invalid";
uint64_t mask = ctx->PAMask >> 36;
- if (!(ctx->hflags & MIPS_HFLAG_ELPA)) {
- goto mthc0_nop;
- }
+ CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
switch (reg) {
case 2:
@@ -4859,7 +4862,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel)
rn = "EntryLo0";
break;
default:
- goto mthc0_nop;
+ goto cp0_unimplemented;
}
break;
case 3:
@@ -4870,7 +4873,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel)
rn = "EntryLo1";
break;
default:
- goto mthc0_nop;
+ goto cp0_unimplemented;
}
break;
case 17:
@@ -4883,7 +4886,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel)
rn = "LLAddr";
break;
default:
- goto mthc0_nop;
+ goto cp0_unimplemented;
}
break;
case 28:
@@ -4897,15 +4900,15 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel)
rn = "TagLo";
break;
default:
- goto mthc0_nop;
+ goto cp0_unimplemented;
}
break;
default:
- goto mthc0_nop;
+ goto cp0_unimplemented;
}
(void)rn; /* avoid a compiler warning */
-mthc0_nop:
+cp0_unimplemented:
LOG_DISAS("mthc0 %s (reg %d sel %d)\n", rn, reg, sel);
}
@@ -4918,13 +4921,6 @@ static inline void gen_mfc0_unimplemented(DisasContext *ctx, TCGv arg)
}
}
-#define CP0_CHECK(c) \
- do { \
- if (!(c)) { \
- goto cp0_unimplemented; \
- } \
- } while (0)
-
static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
{
const char *rn = "invalid";
--
2.1.0
next prev parent reply other threads:[~2016-03-30 8:50 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-03-30 8:49 [Qemu-devel] [PULL v2 00/21] target-mips queue for 2.6 Leon Alrae
2016-03-30 8:49 ` [Qemu-devel] [PULL v2 01/21] hw/mips: implement generic MIPS Coherent Processing System container Leon Alrae
2016-03-30 8:49 ` [Qemu-devel] [PULL v2 02/21] target-mips: add CMGCRBase register Leon Alrae
2016-03-30 8:49 ` [Qemu-devel] [PULL v2 03/21] hw/mips: add initial Global Config Register support Leon Alrae
2016-03-30 8:49 ` [Qemu-devel] [PULL v2 04/21] hw/mips/cps: create GCR block inside CPS Leon Alrae
2016-03-30 8:49 ` [Qemu-devel] [PULL v2 05/21] hw/mips: add initial Cluster Power Controller support Leon Alrae
2016-03-30 8:49 ` [Qemu-devel] [PULL v2 06/21] hw/mips/cps: create CPC block inside CPS Leon Alrae
2016-03-30 8:49 ` [Qemu-devel] [PULL v2 07/21] hw/mips_malta: remove CPUMIPSState from the write_bootloader() Leon Alrae
2016-03-30 8:49 ` [Qemu-devel] [PULL v2 08/21] hw/mips_malta: remove redundant irq and clock init Leon Alrae
2016-03-30 8:49 ` [Qemu-devel] [PULL v2 09/21] hw/mips_malta: move CPU creation to a separate function Leon Alrae
2016-03-30 8:49 ` [Qemu-devel] [PULL v2 10/21] hw/mips_malta: add CPS to Malta board Leon Alrae
2016-03-30 8:49 ` [Qemu-devel] [PULL v2 11/21] target-mips: enable CM GCR in MIPS64R6-generic CPU Leon Alrae
2016-03-30 8:49 ` [Qemu-devel] [PULL v2 12/21] hw/mips: implement ITC Configuration Tags and Storage Cells Leon Alrae
2016-03-30 8:49 ` [Qemu-devel] [PULL v2 13/21] hw/mips: implement ITC Storage - Control View Leon Alrae
2016-03-30 8:49 ` [Qemu-devel] [PULL v2 14/21] hw/mips: implement ITC Storage - Empty/Full Sync and Try Views Leon Alrae
2016-03-30 8:49 ` [Qemu-devel] [PULL v2 15/21] hw/mips: implement ITC Storage - P/V " Leon Alrae
2016-03-30 8:49 ` [Qemu-devel] [PULL v2 16/21] hw/mips: implement ITC Storage - Bypass View Leon Alrae
2016-03-30 8:49 ` [Qemu-devel] [PULL v2 17/21] target-mips: check CP0 enabled for CACHE instruction also in R6 Leon Alrae
2016-03-30 8:49 ` [Qemu-devel] [PULL v2 18/21] target-mips: make ITC Configuration Tags accessible to the CPU Leon Alrae
2016-03-30 8:50 ` [Qemu-devel] [PULL v2 19/21] hw/mips/cps: enable ITU for multithreading processors Leon Alrae
2016-03-30 8:50 ` Leon Alrae [this message]
2016-03-30 8:50 ` [Qemu-devel] [PULL v2 21/21] target-mips: add MAAR, MAARI register Leon Alrae
2016-03-30 16:12 ` [Qemu-devel] [PULL v2 00/21] target-mips queue for 2.6 Peter Maydell
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1459327802-5102-21-git-send-email-leon.alrae@imgtec.com \
--to=leon.alrae@imgtec.com \
--cc=qemu-devel@nongnu.org \
--cc=yongbok.kim@imgtec.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).