[Qemu-devel] [PULL for-2.6] tcg/mips fix

[Qemu-devel] [PULL for-2.6] tcg/mips fix

[Richard Henderson]

One compilation error to be fixed.


r~


The following changes since commit 43b0ea1a41bd0a02debd48a18e0b5460148e3f40:

  bsd-user: Suppress gcc 4.x -Wpointer-sign (included in -Wall) warning (2016-04-05 17:49:41 +0100)

are available in the git repository at:

  git://github.com/rth7680/qemu.git tags/pull-tcg-20160405

for you to fetch changes up to 2dc7553d0c0a3915c649e1a91b0f0be70b4674b3:

  tcg/mips: Fix type of tcg_target_reg_alloc_order[] (2016-04-05 12:47:47 -0700)

----------------------------------------------------------------
tcg/mips compilation fix

----------------------------------------------------------------
James Hogan (1):
      tcg/mips: Fix type of tcg_target_reg_alloc_order[]

 tcg/mips/tcg-target.inc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

[Qemu-devel] [PULL for-2.6] tcg/mips: Fix type of tcg_target_reg_alloc_order[]

[Richard Henderson]

From: James Hogan <james.hogan@imgtec.com>

The MIPS TCG backend is the only one to have
tcg_target_reg_alloc_order[] elements of type TCGReg rather than int.
This resulted in commit 91478cefaaf2 ("tcg: Allocate indirect_base
temporaries in a different order") breaking the build on MIPS since the
type differed from indirect_reg_alloc_order[]:

tcg/tcg.c:1725:44: error: pointer type mismatch in conditional expression [-Werror]
     order = rev ? indirect_reg_alloc_order : tcg_target_reg_alloc_order;
                                            ^

Make it an array of ints to fix the build and match other architectures.

Fixes: 91478cefaaf2 ("tcg: Allocate indirect_base temporaries in a different order")
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Acked-by: Aurelien Jarno <aurelien@aurel32.net>
Message-Id: <1459522179-6584-1-git-send-email-james.hogan@imgtec.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/mips/tcg-target.inc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c
index 297bd00..682e198 100644
--- a/tcg/mips/tcg-target.inc.c
+++ b/tcg/mips/tcg-target.inc.c
@@ -76,7 +76,7 @@ static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
 #define TCG_TMP1  TCG_REG_T9
 
 /* check if we really need so many registers :P */
-static const TCGReg tcg_target_reg_alloc_order[] = {
+static const int tcg_target_reg_alloc_order[] = {
     /* Call saved registers.  */
     TCG_REG_S0,
     TCG_REG_S1,
-- 
2.5.5

Re: [Qemu-devel] [PULL for-2.6] tcg/mips fix

[Peter Maydell]

On 5 April 2016 at 20:51, Richard Henderson <rth@twiddle.net> wrote:
> One compilation error to be fixed.
>
>
> r~
>
>
> The following changes since commit 43b0ea1a41bd0a02debd48a18e0b5460148e3f40:
>
>   bsd-user: Suppress gcc 4.x -Wpointer-sign (included in -Wall) warning (2016-04-05 17:49:41 +0100)
>
> are available in the git repository at:
>
>   git://github.com/rth7680/qemu.git tags/pull-tcg-20160405
>
> for you to fetch changes up to 2dc7553d0c0a3915c649e1a91b0f0be70b4674b3:
>
>   tcg/mips: Fix type of tcg_target_reg_alloc_order[] (2016-04-05 12:47:47 -0700)
>
> ----------------------------------------------------------------
> tcg/mips compilation fix
>
> ----------------------------------------------------------------
> James Hogan (1):
>       tcg/mips: Fix type of tcg_target_reg_alloc_order[]
>
>  tcg/mips/tcg-target.inc.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

Applied, thanks.

-- PMM