From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57200) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1asVsk-0003cb-1U for qemu-devel@nongnu.org; Tue, 19 Apr 2016 09:39:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1asVsj-0000jg-5Y for qemu-devel@nongnu.org; Tue, 19 Apr 2016 09:39:57 -0400 Received: from mail-wm0-x243.google.com ([2a00:1450:400c:c09::243]:34558) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1asVsi-0000jO-Oj for qemu-devel@nongnu.org; Tue, 19 Apr 2016 09:39:56 -0400 Received: by mail-wm0-x243.google.com with SMTP id n3so5311378wmn.1 for ; Tue, 19 Apr 2016 06:39:56 -0700 (PDT) From: Alvise Rigo Date: Tue, 19 Apr 2016 15:39:30 +0200 Message-Id: <1461073171-22953-14-git-send-email-a.rigo@virtualopensystems.com> In-Reply-To: <1461073171-22953-1-git-send-email-a.rigo@virtualopensystems.com> References: <1461073171-22953-1-git-send-email-a.rigo@virtualopensystems.com> Subject: [Qemu-devel] [RFC v8 13/14] target-arm: cpu64: use custom set_excl hook List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, mttcg@listserver.greensocs.com Cc: jani.kokkonen@huawei.com, claudio.fontana@huawei.com, tech@virtualopensystems.com, alex.bennee@linaro.org, pbonzini@redhat.com, rth@twiddle.net, serge.fdrv@gmail.com, Alvise Rigo , Peter Maydell , "open list:ARM" In aarch64 the LDXP/STXP instructions allow to perform up to 128 bits exclusive accesses. However, due to a softmmu limitation, such wide accesses are not allowed. To workaround this limitation, we need to support LoadLink instructions that cover at least 128 consecutive bits (see the next patch for more details). Suggested-by: Jani Kokkonen Suggested-by: Claudio Fontana Signed-off-by: Alvise Rigo --- target-arm/cpu64.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c index cc177bb..1d45e66 100644 --- a/target-arm/cpu64.c +++ b/target-arm/cpu64.c @@ -287,6 +287,13 @@ static void aarch64_cpu_set_pc(CPUState *cs, vaddr value) } } +static void aarch64_set_excl_range(CPUState *cpu, hwaddr addr, hwaddr size) +{ + cpu->excl_protected_range.begin = addr; + /* At least cover 128 bits for a STXP access (two paired doublewords case)*/ + cpu->excl_protected_range.end = addr + 16; +} + static void aarch64_cpu_class_init(ObjectClass *oc, void *data) { CPUClass *cc = CPU_CLASS(oc); @@ -297,6 +304,7 @@ static void aarch64_cpu_class_init(ObjectClass *oc, void *data) cc->gdb_write_register = aarch64_cpu_gdb_write_register; cc->gdb_num_core_regs = 34; cc->gdb_core_xml_file = "aarch64-core.xml"; + cc->cpu_set_excl_protected_range = aarch64_set_excl_range; } static void aarch64_cpu_register(const ARMCPUInfo *info) -- 2.8.0