From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47118) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1atddx-0008AO-Ug for qemu-devel@nongnu.org; Fri, 22 Apr 2016 12:09:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1atddv-0008Gn-4b for qemu-devel@nongnu.org; Fri, 22 Apr 2016 12:09:21 -0400 Received: from mail-lf0-x235.google.com ([2a00:1450:4010:c07::235]:33192) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1atddu-0008GW-Hr for qemu-devel@nongnu.org; Fri, 22 Apr 2016 12:09:19 -0400 Received: by mail-lf0-x235.google.com with SMTP id e190so82101981lfe.0 for ; Fri, 22 Apr 2016 09:09:18 -0700 (PDT) From: Sergey Fedorov Date: Fri, 22 Apr 2016 19:08:49 +0300 Message-Id: <1461341333-19646-8-git-send-email-sergey.fedorov@linaro.org> In-Reply-To: <1461341333-19646-1-git-send-email-sergey.fedorov@linaro.org> References: <1461341333-19646-1-git-send-email-sergey.fedorov@linaro.org> Subject: [Qemu-devel] [PATCH v2 07/11] tcg/arm: Make direct jump patching thread-safe List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , Sergey Fedorov , Paolo Bonzini , Peter Crosthwaite , Richard Henderson , Sergey Fedorov , Andrzej Zaborowski , qemu-arm@nongnu.org From: Sergey Fedorov Ensure direct jump patching in ARM is atomic by using atomic_read()/atomic_set() for code patching. Signed-off-by: Sergey Fedorov Signed-off-by: Sergey Fedorov --- Changes in v 2: * Add tcg_debug_assert() to check offset * Use deposit32() for insturction patching include/exec/exec-all.h | 25 ++----------------------- tcg/arm/tcg-target.inc.c | 18 ++++++++++++++++++ 2 files changed, 20 insertions(+), 23 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index e18cc24e50f0..6a054ee720a8 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -327,29 +327,8 @@ static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr) void aarch64_tb_set_jmp_target(uintptr_t jmp_addr, uintptr_t addr); #define tb_set_jmp_target1 aarch64_tb_set_jmp_target #elif defined(__arm__) -static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr) -{ -#if !QEMU_GNUC_PREREQ(4, 1) - register unsigned long _beg __asm ("a1"); - register unsigned long _end __asm ("a2"); - register unsigned long _flg __asm ("a3"); -#endif - - /* we could use a ldr pc, [pc, #-4] kind of branch and avoid the flush */ - *(uint32_t *)jmp_addr = - (*(uint32_t *)jmp_addr & ~0xffffff) - | (((addr - (jmp_addr + 8)) >> 2) & 0xffffff); - -#if QEMU_GNUC_PREREQ(4, 1) - __builtin___clear_cache((char *) jmp_addr, (char *) jmp_addr + 4); -#else - /* flush icache */ - _beg = jmp_addr; - _end = jmp_addr + 4; - _flg = 0; - __asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg)); -#endif -} +void arm_tb_set_jmp_target(uintptr_t jmp_addr, uintptr_t addr); +#define tb_set_jmp_target1 arm_tb_set_jmp_target #elif defined(__sparc__) || defined(__mips__) void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr); #else diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c index 3edf6a6f971c..2750610a54f1 100644 --- a/tcg/arm/tcg-target.inc.c +++ b/tcg/arm/tcg-target.inc.c @@ -121,6 +121,14 @@ static inline void reloc_pc24(tcg_insn_unit *code_ptr, tcg_insn_unit *target) *code_ptr = (*code_ptr & ~0xffffff) | (offset & 0xffffff); } +static inline void reloc_pc24_atomic(tcg_insn_unit *code_ptr, tcg_insn_unit *target) +{ + ptrdiff_t offset = (tcg_ptr_byte_diff(target, code_ptr) - 8) >> 2; + tcg_insn_unit insn = atomic_read(code_ptr); + tcg_debug_assert(offset == sextract32(offset, 0, 24)); + atomic_set(code_ptr, deposit32(insn, 0, 24, offset)); +} + static void patch_reloc(tcg_insn_unit *code_ptr, int type, intptr_t value, intptr_t addend) { @@ -1038,6 +1046,16 @@ static void tcg_out_call(TCGContext *s, tcg_insn_unit *addr) } } +void arm_tb_set_jmp_target(uintptr_t jmp_addr, uintptr_t addr) +{ + tcg_insn_unit *code_ptr = (tcg_insn_unit *)jmp_addr; + tcg_insn_unit *target = (tcg_insn_unit *)addr; + + /* we could use a ldr pc, [pc, #-4] kind of branch and avoid the flush */ + reloc_pc24_atomic(code_ptr, target); + flush_icache_range(jmp_addr, jmp_addr + 4); +} + static inline void tcg_out_goto_label(TCGContext *s, int cond, TCGLabel *l) { if (l->has_value) { -- 2.8.1