From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41750) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1avg2R-0004mL-0J for qemu-devel@nongnu.org; Thu, 28 Apr 2016 03:07:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1avg2N-0007jt-PS for qemu-devel@nongnu.org; Thu, 28 Apr 2016 03:07:02 -0400 Received: from mx1.redhat.com ([209.132.183.28]:47577) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1avg2N-0007jp-KS for qemu-devel@nongnu.org; Thu, 28 Apr 2016 03:06:59 -0400 From: Peter Xu Date: Thu, 28 Apr 2016 15:05:43 +0800 Message-Id: <1461827144-6937-18-git-send-email-peterx@redhat.com> In-Reply-To: <1461827144-6937-1-git-send-email-peterx@redhat.com> References: <1461827144-6937-1-git-send-email-peterx@redhat.com> Subject: [Qemu-devel] [PATCH v5 17/18] ioapic: keep RO bits for IOAPIC entry List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: imammedo@redhat.com, rth@twiddle.net, ehabkost@redhat.com, jasowang@redhat.com, marcel@redhat.com, mst@redhat.com, pbonzini@redhat.com, jan.kiszka@web.de, rkrcmar@redhat.com, alex.williamson@redhat.com, wexu@redhat.com, peterx@redhat.com Currently IOAPIC RO bits can be written. To be better aligned with hardware, we should let them read-only. Signed-off-by: Peter Xu --- hw/intc/ioapic.c | 4 ++++ include/hw/i386/ioapic_internal.h | 5 +++++ 2 files changed, 9 insertions(+) diff --git a/hw/intc/ioapic.c b/hw/intc/ioapic.c index b41ab89..d7ebb5c 100644 --- a/hw/intc/ioapic.c +++ b/hw/intc/ioapic.c @@ -307,6 +307,7 @@ ioapic_mem_write(void *opaque, hwaddr addr, uint64_t val, default: index = (s->ioregsel - IOAPIC_REG_REDTBL_BASE) >> 1; if (index >= 0 && index < IOAPIC_NUM_PINS) { + uint64_t ro_bits = s->ioredtbl[index] & IOAPIC_RO_BITS; if (s->ioregsel & 1) { s->ioredtbl[index] &= 0xffffffff; s->ioredtbl[index] |= (uint64_t)val << 32; @@ -314,6 +315,9 @@ ioapic_mem_write(void *opaque, hwaddr addr, uint64_t val, s->ioredtbl[index] &= ~0xffffffffULL; s->ioredtbl[index] |= val; } + /* restore RO bits */ + s->ioredtbl[index] &= IOAPIC_RW_BITS; + s->ioredtbl[index] |= ro_bits; ioapic_service(s); } } diff --git a/include/hw/i386/ioapic_internal.h b/include/hw/i386/ioapic_internal.h index d279f2d..31dafb3 100644 --- a/include/hw/i386/ioapic_internal.h +++ b/include/hw/i386/ioapic_internal.h @@ -48,6 +48,11 @@ #define IOAPIC_LVT_DEST_MODE (1 << IOAPIC_LVT_DEST_MODE_SHIFT) #define IOAPIC_LVT_DELIV_MODE (7 << IOAPIC_LVT_DELIV_MODE_SHIFT) +/* Bits that are read-only for IOAPIC entry */ +#define IOAPIC_RO_BITS (IOAPIC_LVT_REMOTE_IRR | \ + IOAPIC_LVT_DELIV_STATUS) +#define IOAPIC_RW_BITS (~(uint64_t)IOAPIC_RO_BITS) + #define IOAPIC_TRIGGER_EDGE 0 #define IOAPIC_TRIGGER_LEVEL 1 -- 2.4.3