From: Laurent Vivier <laurent@vivier.eu>
To: qemu-devel@nongnu.org
Cc: gerg@uclinux.org, schwab@linux-m68k.org, agraf@suse.de,
rth@twiddle.net, Laurent Vivier <laurent@vivier.eu>
Subject: [Qemu-devel] [PATCH 22/52] target-m68k: Introduce DisasCompare
Date: Wed, 4 May 2016 22:12:02 +0200 [thread overview]
Message-ID: <1462392752-17703-23-git-send-email-laurent@vivier.eu> (raw)
In-Reply-To: <1462392752-17703-1-git-send-email-laurent@vivier.eu>
From: Richard Henderson <rth@twiddle.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
---
target-m68k/translate.c | 85 +++++++++++++++++++++++++++++++++++--------------
1 file changed, 61 insertions(+), 24 deletions(-)
diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index c3d7318..efd4d9c 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -756,8 +756,15 @@ static TCGv gen_ea(CPUM68KState *env, DisasContext *s, uint16_t insn,
return NULL_QREG;
}
-/* This generates a conditional branch, clobbering all temporaries. */
-static void gen_jmpcc(DisasContext *s, int cond, TCGLabel *l1)
+typedef struct {
+ TCGCond tcond;
+ bool g1;
+ bool g2;
+ TCGv v1;
+ TCGv v2;
+} DisasCompare;
+
+static void gen_cc_cond(DisasCompare *c, DisasContext *s, int cond)
{
TCGv tmp, tmp2;
TCGCond tcond;
@@ -765,61 +772,92 @@ static void gen_jmpcc(DisasContext *s, int cond, TCGLabel *l1)
/* TODO: Optimize compare/branch pairs rather than always flushing
flag state to CC_OP_FLAGS. */
gen_flush_flags(s);
- update_cc_op(s);
+
+ c->g1 = 1;
+ c->g2 = 0;
+ c->v2 = tcg_const_i32(0);
+
switch (cond) {
case 0: /* T */
- tcg_gen_br(l1);
- return;
case 1: /* F */
- return;
+ c->v1 = c->v2;
+ tcond = TCG_COND_NEVER;
+ break;
case 2: /* HI (!C && !Z) -> !(C || Z)*/
case 3: /* LS (C || Z) */
- tmp = tcg_temp_new();
- tcg_gen_setcondi_i32(TCG_COND_EQ, tmp, QREG_CC_Z, 0);
+ c->v1 = tmp = tcg_temp_new();
+ c->g1 = 0;
+ tcg_gen_setcond_i32(TCG_COND_EQ, tmp, QREG_CC_Z, c->v2);
tcg_gen_or_i32(tmp, tmp, QREG_CC_C);
- tcond = (cond & 1 ? TCG_COND_NE: TCG_COND_EQ);
+ tcond = TCG_COND_NE;
break;
case 4: /* CC (!C) */
case 5: /* CS (C) */
- tmp = QREG_CC_C;
- tcond = (cond & 1 ? TCG_COND_NE : TCG_COND_EQ);
+ c->v1 = QREG_CC_C;
+ tcond = TCG_COND_NE;
break;
case 6: /* NE (!Z) */
case 7: /* EQ (Z) */
- tmp = QREG_CC_Z;
- tcond = (cond & 1 ? TCG_COND_EQ : TCG_COND_NE);
+ c->v1 = QREG_CC_Z;
+ tcond = TCG_COND_EQ;
break;
case 8: /* VC (!V) */
case 9: /* VS (V) */
- tmp = QREG_CC_V;
- tcond = (cond & 1 ? TCG_COND_LT : TCG_COND_GE);
+ c->v1 = QREG_CC_V;
+ tcond = TCG_COND_LT;
break;
case 10: /* PL (!N) */
case 11: /* MI (N) */
- tmp = QREG_CC_N;
- tcond = (cond & 1 ? TCG_COND_LT : TCG_COND_GE);
+ c->v1 = QREG_CC_N;
+ tcond = TCG_COND_LT;
break;
case 12: /* GE (!(N ^ V)) */
case 13: /* LT (N ^ V) */
- tmp = tcg_temp_new();
+ c->v1 = tmp = tcg_temp_new();
+ c->g1 = 0;
tcg_gen_xor_i32(tmp, QREG_CC_N, QREG_CC_V);
- tcond = (cond & 1 ? TCG_COND_LT : TCG_COND_GE);
+ tcond = TCG_COND_LT;
break;
case 14: /* GT (!(Z || (N ^ V))) */
case 15: /* LE (Z || (N ^ V)) */
- tmp = tcg_temp_new();
- tcg_gen_setcondi_i32(TCG_COND_EQ, tmp, QREG_CC_Z, 0);
+ c->v1 = tmp = tcg_temp_new();
+ c->g1 = 0;
+ tcg_gen_setcond_i32(TCG_COND_EQ, tmp, QREG_CC_Z, c->v2);
tcg_gen_neg_i32(tmp, tmp);
tmp2 = tcg_temp_new();
tcg_gen_xor_i32(tmp2, QREG_CC_N, QREG_CC_V);
tcg_gen_or_i32(tmp, tmp, tmp2);
- tcond = (cond & 1 ? TCG_COND_LT : TCG_COND_GE);
+ tcg_temp_free(tmp2);
+ tcond = TCG_COND_LT;
break;
default:
/* Should ever happen. */
abort();
}
- tcg_gen_brcondi_i32(tcond, tmp, 0, l1);
+ if ((cond & 1) == 0) {
+ tcond = tcg_invert_cond(tcond);
+ }
+ c->tcond = tcond;
+}
+
+static void free_cond(DisasCompare *c)
+{
+ if (!c->g1) {
+ tcg_temp_free(c->v1);
+ }
+ if (!c->g2) {
+ tcg_temp_free(c->v2);
+ }
+}
+
+static void gen_jmpcc(DisasContext *s, int cond, TCGLabel *l1)
+{
+ DisasCompare c;
+
+ gen_cc_cond(&c, s, cond);
+ update_cc_op(s);
+ tcg_gen_brcond_i32(c.tcond, c.v1, c.v2, l1);
+ free_cond(&c);
}
DISAS_INSN(scc)
@@ -1674,7 +1712,6 @@ DISAS_INSN(branch)
/* bsr */
gen_push(s, tcg_const_i32(s->pc));
}
- update_cc_op(s);
if (op > 1) {
/* Bcc */
l1 = gen_new_label();
--
2.5.5
next prev parent reply other threads:[~2016-05-04 20:15 UTC|newest]
Thread overview: 131+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-05-04 20:11 [Qemu-devel] [PATCH 00/52] 680x0 instructions emulation Laurent Vivier
2016-05-04 20:11 ` [Qemu-devel] [PATCH 01/52] target-m68k: fix DEBUG_DISPATCH Laurent Vivier
2016-05-06 16:34 ` Richard Henderson
2016-05-04 20:11 ` [Qemu-devel] [PATCH 02/52] target-m68k: Build the opcode table only once to avoid multithreading issues Laurent Vivier
2016-05-06 16:35 ` Richard Henderson
2016-05-04 20:11 ` [Qemu-devel] [PATCH 03/52] target-m68k: define m680x0 CPUs and features Laurent Vivier
2016-05-06 16:35 ` Richard Henderson
2016-05-04 20:11 ` [Qemu-devel] [PATCH 04/52] target-m68k: manage scaled index Laurent Vivier
2016-05-06 16:36 ` Richard Henderson
2016-05-04 20:11 ` [Qemu-devel] [PATCH 05/52] target-m68k: introduce read_imXX() functions Laurent Vivier
2016-05-06 16:36 ` Richard Henderson
2016-05-04 20:11 ` [Qemu-devel] [PATCH 06/52] target-m68k: set disassembler mode to 680x0 or coldfire Laurent Vivier
2016-05-06 16:37 ` Richard Henderson
2016-05-04 20:11 ` [Qemu-devel] [PATCH 07/52] target-m68k: add bkpt instruction Laurent Vivier
2016-05-06 16:42 ` Richard Henderson
2016-05-07 7:08 ` Laurent Vivier
2016-05-04 20:11 ` [Qemu-devel] [PATCH 08/52] target-m68k: define operand sizes Laurent Vivier
2016-05-06 16:43 ` Richard Henderson
2016-05-04 20:11 ` [Qemu-devel] [PATCH 09/52] target-m68k: set PAGE_BITS to 12 for m68k Laurent Vivier
2016-05-06 16:44 ` Richard Henderson
2016-05-04 20:11 ` [Qemu-devel] [PATCH 10/52] target-m68k: REG() macro cleanup Laurent Vivier
2016-05-06 16:44 ` Richard Henderson
2016-05-04 20:11 ` [Qemu-devel] [PATCH 11/52] target-m68k: allow to update flags with operation on words and bytes Laurent Vivier
2016-05-06 16:45 ` Richard Henderson
2016-05-07 7:19 ` Laurent Vivier
2016-05-04 20:11 ` [Qemu-devel] [PATCH 12/52] target-m68k: Replace helper_xflag_lt with setcond Laurent Vivier
2016-05-04 20:11 ` [Qemu-devel] [PATCH 13/52] target-m68k: update CPU flags management Laurent Vivier
2016-05-06 16:46 ` Richard Henderson
2016-05-04 20:11 ` [Qemu-devel] [PATCH 14/52] target-m68k: update move to/from ccr/sr Laurent Vivier
2016-05-06 16:47 ` Richard Henderson
2016-05-04 20:11 ` [Qemu-devel] [PATCH 15/52] target-m68k: don't update cc_dest in helpers Laurent Vivier
2016-05-06 16:47 ` Richard Henderson
2016-05-04 20:11 ` [Qemu-devel] [PATCH 16/52] target-m68k: update CPU flags management Laurent Vivier
2016-05-06 16:47 ` Richard Henderson
2016-05-04 20:11 ` [Qemu-devel] [PATCH 17/52] target-m68k: Print flags properly Laurent Vivier
2016-05-04 20:11 ` [Qemu-devel] [PATCH 18/52] target-m68k: Some fixes to SR and flags management Laurent Vivier
2016-05-06 16:49 ` Richard Henderson
2016-05-04 20:11 ` [Qemu-devel] [PATCH 19/52] target-m68k: terminate cpu dump with newline Laurent Vivier
2016-05-06 16:49 ` Richard Henderson
2016-05-06 17:41 ` Andreas Schwab
2016-05-04 20:12 ` [Qemu-devel] [PATCH 20/52] target-m68k: Remove incorrect clearing of cc_x Laurent Vivier
2016-05-04 20:12 ` [Qemu-devel] [PATCH 21/52] target-m68k: Reorg flags handling Laurent Vivier
2016-05-06 16:51 ` Richard Henderson
2016-05-04 20:12 ` Laurent Vivier [this message]
2016-05-04 20:12 ` [Qemu-devel] [PATCH 23/52] target-m68k: Use setcond for scc Laurent Vivier
2016-05-04 20:12 ` [Qemu-devel] [PATCH 24/52] target-m68k: Optimize some comparisons Laurent Vivier
2016-05-04 20:12 ` [Qemu-devel] [PATCH 25/52] target-m68k: Optimize gen_flush_flags Laurent Vivier
2016-05-04 20:12 ` [Qemu-devel] [PATCH 26/52] target-m68k: Inline shifts Laurent Vivier
2016-05-06 16:53 ` Richard Henderson
2016-05-04 20:12 ` [Qemu-devel] [PATCH 27/52] target-m68k: Inline addx, subx, negx Laurent Vivier
2016-05-04 20:12 ` [Qemu-devel] [PATCH 28/52] target-m68k: add addx/subx/negx ops Laurent Vivier
2016-05-06 17:11 ` Richard Henderson
2016-05-04 20:12 ` [Qemu-devel] [PATCH 29/52] target-m68k: factorize flags computing Laurent Vivier
2016-05-06 17:11 ` Richard Henderson
2016-05-04 20:12 ` [Qemu-devel] [PATCH 30/52] target-m68k: add scc/dbcc Laurent Vivier
2016-05-06 17:18 ` Richard Henderson
2016-05-06 17:44 ` Andreas Schwab
2016-05-04 20:12 ` [Qemu-devel] [PATCH 31/52] target-m68k: some bit ops cleanup Laurent Vivier
2016-05-06 17:20 ` Richard Henderson
2016-05-04 20:12 ` [Qemu-devel] [PATCH 32/52] target-m68k: bitfield ops Laurent Vivier
2016-05-06 19:11 ` Richard Henderson
2016-05-04 21:08 ` [Qemu-devel] [PATCH 33/52] target-m68k: inline divu/divs Laurent Vivier
2016-05-04 21:08 ` [Qemu-devel] [PATCH 34/52] target-m68k: add 64bit mull Laurent Vivier
2016-05-06 19:48 ` Richard Henderson
2016-05-04 21:08 ` [Qemu-devel] [PATCH 35/52] target-m68k: inline rotate ops Laurent Vivier
2016-05-06 20:28 ` Richard Henderson
2016-05-04 21:08 ` [Qemu-devel] [PATCH 36/52] target-m68k: inline shift ops Laurent Vivier
2016-05-06 20:53 ` Richard Henderson
2016-05-04 21:08 ` [Qemu-devel] [PATCH 37/52] target-m68k: add cas/cas2 ops Laurent Vivier
2016-05-06 21:29 ` Richard Henderson
2016-05-04 21:08 ` [Qemu-devel] [PATCH 38/52] target-m68k: add linkl Laurent Vivier
2016-05-06 21:30 ` Richard Henderson
2016-05-04 21:08 ` [Qemu-devel] [PATCH 39/52] target-m68k: movem Laurent Vivier
2016-05-06 21:45 ` Richard Henderson
2016-05-06 19:44 ` [Qemu-devel] [PATCH 33/52] target-m68k: inline divu/divs Richard Henderson
2016-05-04 21:20 ` [Qemu-devel] [PATCH 40/52] target-m68k: add exg ops Laurent Vivier
2016-05-04 21:20 ` [Qemu-devel] [PATCH 41/52] target-m68k: add addressing modes to not Laurent Vivier
2016-05-06 21:47 ` Richard Henderson
2016-05-04 21:20 ` [Qemu-devel] [PATCH 42/52] target-m68k: eor can manage word and byte operands Laurent Vivier
2016-05-06 21:48 ` Richard Henderson
2016-05-04 21:21 ` [Qemu-devel] [PATCH 43/52] target-m68k: or " Laurent Vivier
2016-05-06 21:49 ` Richard Henderson
2016-05-04 21:21 ` [Qemu-devel] [PATCH 44/52] target-m68k: and " Laurent Vivier
2016-05-06 21:49 ` Richard Henderson
2016-05-04 21:21 ` [Qemu-devel] [PATCH 45/52] target-m68k: suba/adda can manage word operand Laurent Vivier
2016-05-06 21:50 ` Richard Henderson
2016-05-04 21:21 ` [Qemu-devel] [PATCH 46/52] target-m68k: introduce byte and word cc_ops Laurent Vivier
2016-05-06 21:53 ` Richard Henderson
2016-05-04 21:21 ` [Qemu-devel] [PATCH 47/52] target-m68k: add addressing modes to neg Laurent Vivier
2016-05-06 21:54 ` Richard Henderson
2016-05-04 21:21 ` [Qemu-devel] [PATCH 48/52] target-m68k: add/sub manage word and byte operands Laurent Vivier
2016-05-06 21:57 ` Richard Henderson
2016-05-04 21:21 ` [Qemu-devel] [PATCH 49/52] target-m68k: cmp manages word and bytes operands Laurent Vivier
2016-05-06 21:57 ` Richard Henderson
2016-05-04 21:21 ` [Qemu-devel] [PATCH 50/52] target-m68k: immediate ops manage word and byte operands Laurent Vivier
2016-05-06 21:59 ` Richard Henderson
2016-05-04 21:21 ` [Qemu-devel] [PATCH 51/52] target-m68k: add cmpm Laurent Vivier
2016-05-06 22:00 ` Richard Henderson
2016-05-07 19:01 ` Laurent Vivier
2016-05-07 21:50 ` Peter Maydell
2016-05-08 9:07 ` Laurent Vivier
2016-05-08 10:44 ` Peter Maydell
2016-05-04 21:21 ` [Qemu-devel] [PATCH 52/52] target-m68k: sr/ccr cleanup Laurent Vivier
2016-05-06 22:02 ` Richard Henderson
2016-05-06 21:47 ` [Qemu-devel] [PATCH 40/52] target-m68k: add exg ops Richard Henderson
2016-05-06 9:35 ` [Qemu-devel] [PATCH 00/52] 680x0 instructions emulation Andreas Schwab
2016-05-06 9:54 ` Laurent Vivier
2016-05-06 10:15 ` Andreas Schwab
2016-05-06 11:40 ` John Paul Adrian Glaubitz
2016-05-06 12:44 ` Andreas Schwab
2016-05-06 13:02 ` John Paul Adrian Glaubitz
2016-05-06 13:24 ` Andreas Schwab
2016-05-06 13:45 ` John Paul Adrian Glaubitz
2016-05-06 13:48 ` Andreas Schwab
2016-05-06 13:53 ` John Paul Adrian Glaubitz
2016-05-06 13:53 ` Laurent Vivier
2016-05-06 13:58 ` Andreas Schwab
2016-05-06 14:25 ` Andreas Schwab
2016-05-06 14:47 ` Andreas Schwab
2016-05-06 11:40 ` John Paul Adrian Glaubitz
2016-05-06 11:45 ` Alexander Graf
2016-05-06 11:57 ` Laurent Vivier
2016-05-06 12:03 ` Peter Maydell
2016-05-12 21:17 ` John Paul Adrian Glaubitz
2016-05-12 21:20 ` Laurent Vivier
[not found] ` <D2F89431-FF87-456A-A628-7F8ADCDDAFC7@suse.de>
2016-05-12 21:25 ` John Paul Adrian Glaubitz
[not found] ` <C662446E-C86D-4838-83C5-14E8E6C52D2A@suse.de>
2016-05-12 21:32 ` John Paul Adrian Glaubitz
2016-05-12 21:30 ` Laurent Vivier
2016-05-06 10:06 ` Alexander Graf
2016-05-06 10:30 ` [Qemu-devel] [PATCH] MAINTAINERS: update M68K entry Laurent Vivier
2016-05-12 7:55 ` Thomas Huth
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