From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45588) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ay444-0008Gw-12 for qemu-devel@nongnu.org; Wed, 04 May 2016 17:10:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ay43s-0000Mq-7D for qemu-devel@nongnu.org; Wed, 04 May 2016 17:10:30 -0400 Received: from smtp1-g21.free.fr ([212.27.42.1]:31253) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ay43r-0000Ge-Th for qemu-devel@nongnu.org; Wed, 04 May 2016 17:10:24 -0400 From: Laurent Vivier Date: Wed, 4 May 2016 23:08:37 +0200 Message-Id: <1462396135-20925-2-git-send-email-laurent@vivier.eu> In-Reply-To: <1462396135-20925-1-git-send-email-laurent@vivier.eu> References: <1462392752-17703-1-git-send-email-laurent@vivier.eu> <1462396135-20925-1-git-send-email-laurent@vivier.eu> Subject: [Qemu-devel] [PATCH 34/52] target-m68k: add 64bit mull List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: rth@twiddle.net, schwab@linux-m68k.org, gerg@uclinux.org, agraf@suse.de, Laurent Vivier Signed-off-by: Laurent Vivier --- target-m68k/translate.c | 54 ++++++++++++++++++++++++++++++++++++++----------- 1 file changed, 42 insertions(+), 12 deletions(-) diff --git a/target-m68k/translate.c b/target-m68k/translate.c index b47f9c1..1d05c6a 100644 --- a/target-m68k/translate.c +++ b/target-m68k/translate.c @@ -2128,24 +2128,54 @@ DISAS_INSN(tas) DISAS_INSN(mull) { uint16_t ext; - TCGv reg; TCGv src1; - TCGv dest; + int sign; - /* The upper 32 bits of the product are discarded, so - muls.l and mulu.l are functionally equivalent. */ ext = read_im16(env, s); - if (ext & 0x87ff) { - gen_exception(s, s->pc - 4, EXCP_UNSUPPORTED); + + sign = ext & 0x800; + + if (ext & 0x400) { + if (!m68k_feature(s->env, M68K_FEATURE_QUAD_MULDIV)) { + gen_exception(s, s->pc - 4, EXCP_UNSUPPORTED); + return; + } + + SRC_EA(env, src1, OS_LONG, 0, NULL); + + if (sign) { + tcg_gen_muls2_i32(DREG(ext, 12), DREG(ext, 0), src1, DREG(ext, 12)); + } else { + tcg_gen_mulu2_i32(DREG(ext, 12), DREG(ext, 0), src1, DREG(ext, 12)); + } + + tcg_gen_movi_i32(QREG_CC_V, 0); + tcg_gen_mov_i32(QREG_CC_C, QREG_CC_V); + tcg_gen_mov_i32(QREG_CC_N, DREG(ext, 0)); + tcg_gen_or_i32(QREG_CC_Z, DREG(ext, 12), DREG(ext, 0)); + + set_cc_op(s, CC_OP_FLAGS); return; } - reg = DREG(ext, 12); SRC_EA(env, src1, OS_LONG, 0, NULL); - dest = tcg_temp_new(); - tcg_gen_mul_i32(dest, src1, reg); - tcg_gen_mov_i32(reg, dest); - /* Unlike m68k, coldfire always clears the overflow bit. */ - gen_logic_cc(s, dest, OS_LONG); + if (m68k_feature(s->env, M68K_FEATURE_M68000)) { + if (sign) { + tcg_gen_muls2_i32(QREG_CC_N, QREG_CC_V, src1, DREG(ext, 12)); + } else { + tcg_gen_mulu2_i32(QREG_CC_N, QREG_CC_V, src1, DREG(ext, 12)); + } + tcg_gen_mov_i32(DREG(ext, 12), QREG_CC_N); + + tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N); + tcg_gen_movi_i32(QREG_CC_C, 0); + + set_cc_op(s, CC_OP_FLAGS); + } else { + /* The upper 32 bits of the product are discarded, so + muls.l and mulu.l are functionally equivalent. */ + tcg_gen_mul_i32(DREG(ext, 12), src1, DREG(ext, 12)); + gen_logic_cc(s, DREG(ext, 12), OS_LONG); + } } DISAS_INSN(link) -- 2.5.5