From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51165) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ay4Ex-0000GV-NF for qemu-devel@nongnu.org; Wed, 04 May 2016 17:21:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ay4El-0006NC-TX for qemu-devel@nongnu.org; Wed, 04 May 2016 17:21:46 -0400 Received: from mout.kundenserver.de ([217.72.192.73]:61293) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ay4El-0006GH-KP for qemu-devel@nongnu.org; Wed, 04 May 2016 17:21:39 -0400 From: Laurent Vivier Date: Wed, 4 May 2016 23:20:57 +0200 Message-Id: <1462396869-22424-1-git-send-email-laurent@vivier.eu> In-Reply-To: <1462392752-17703-1-git-send-email-laurent@vivier.eu> References: <1462392752-17703-1-git-send-email-laurent@vivier.eu> Subject: [Qemu-devel] [PATCH 40/52] target-m68k: add exg ops List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: rth@twiddle.net, schwab@linux-m68k.org, gerg@uclinux.org, agraf@suse.de, Laurent Vivier Signed-off-by: Laurent Vivier --- target-m68k/translate.c | 45 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/target-m68k/translate.c b/target-m68k/translate.c index 53c3c41..df5ce94 100644 --- a/target-m68k/translate.c +++ b/target-m68k/translate.c @@ -2721,6 +2721,45 @@ DISAS_INSN(eor) DEST_EA(env, insn, OS_LONG, dest, &addr); } +DISAS_INSN(exg) +{ + TCGv src; + TCGv reg; + TCGv dest; + int exg_mode; + + exg_mode = insn & 0x1f8; + + dest = tcg_temp_new(); + switch (exg_mode) { + case 0x140: + /* exchange Dx and Dy */ + src = DREG(insn, 9); + reg = DREG(insn, 0); + tcg_gen_mov_i32(dest, src); + tcg_gen_mov_i32(src, reg); + tcg_gen_mov_i32(reg, dest); + break; + case 0x148: + /* exchange Ax and Ay */ + src = AREG(insn, 9); + reg = AREG(insn, 0); + tcg_gen_mov_i32(dest, src); + tcg_gen_mov_i32(src, reg); + tcg_gen_mov_i32(reg, dest); + break; + case 0x188: + /* exchange Dx and Ay */ + src = DREG(insn, 9); + reg = AREG(insn, 0); + tcg_gen_mov_i32(dest, src); + tcg_gen_mov_i32(src, reg); + tcg_gen_mov_i32(reg, dest); + break; + } + tcg_temp_free(dest); +} + DISAS_INSN(and) { TCGv src; @@ -4785,6 +4824,12 @@ void register_m68k_insns (CPUM68KState *env) INSN(cmpa, b0c0, f0c0, M68000); INSN(eor, b180, f1c0, CF_ISA_A); BASE(and, c000, f000); + INSN(undef, c140, f1f8, CF_ISA_A); + INSN(exg, c140, f1f8, M68000); + INSN(undef, c148, f1f8, CF_ISA_A); + INSN(exg, c148, f1f8, M68000); + INSN(undef, c188, f1f8, CF_ISA_A); + INSN(exg, c188, f1f8, M68000); BASE(mulw, c0c0, f0c0); INSN(abcd_reg, c100, f1f8, M68000); INSN(abcd_mem, c108, f1f8, M68000); -- 2.5.5