From: Peter Xu <peterx@redhat.com>
To: qemu-devel@nongnu.org
Cc: imammedo@redhat.com, rth@twiddle.net, ehabkost@redhat.com,
jasowang@redhat.com, marcel@redhat.com, mst@redhat.com,
pbonzini@redhat.com, jan.kiszka@web.de, rkrcmar@redhat.com,
alex.williamson@redhat.com, wexu@redhat.com,
davidkiarie4@gmail.com, peterx@redhat.com
Subject: [Qemu-devel] [PATCH v6 12/26] ioapic: introduce ioapic_entry_parse() helper
Date: Thu, 5 May 2016 11:25:47 +0800 [thread overview]
Message-ID: <1462418761-12714-13-git-send-email-peterx@redhat.com> (raw)
In-Reply-To: <1462418761-12714-1-git-send-email-peterx@redhat.com>
Abstract IOAPIC entry parsing logic into a helper function.
Signed-off-by: Peter Xu <peterx@redhat.com>
---
hw/intc/ioapic.c | 110 +++++++++++++++++++++++++++----------------------------
1 file changed, 54 insertions(+), 56 deletions(-)
diff --git a/hw/intc/ioapic.c b/hw/intc/ioapic.c
index 92334a6..d6e88d5 100644
--- a/hw/intc/ioapic.c
+++ b/hw/intc/ioapic.c
@@ -49,18 +49,56 @@ static IOAPICCommonState *ioapics[MAX_IOAPICS];
/* global variable from ioapic_common.c */
extern int ioapic_no;
+struct ioapic_entry_info {
+ /* fields parsed from IOAPIC entries */
+ uint8_t masked;
+ uint8_t trig_mode;
+ uint16_t dest_idx;
+ uint8_t dest_mode;
+ uint8_t delivery_mode;
+ uint8_t vector;
+
+ /* MSI message generated from above parsed fields */
+ uint32_t addr;
+ uint32_t data;
+};
+
+static void ioapic_entry_parse(uint64_t entry, struct ioapic_entry_info *info)
+{
+ bzero(info, sizeof(*info));
+ info->masked = (entry >> IOAPIC_LVT_MASKED_SHIFT) & 1;
+ info->trig_mode = (entry >> IOAPIC_LVT_TRIGGER_MODE_SHIFT) & 1;
+ /*
+ * By default, this would be dest_id[8] + reserved[8]. When IR
+ * is enabled, this would be interrupt_index[15] +
+ * interrupt_format[1]. This field never means anything, but
+ * only used to generate corresponding MSI.
+ */
+ info->dest_idx = (entry >> IOAPIC_LVT_DEST_IDX_SHIFT) & 0xffff;
+ info->dest_mode = (entry >> IOAPIC_LVT_DEST_MODE_SHIFT) & 1;
+ info->delivery_mode = (entry >> IOAPIC_LVT_DELIV_MODE_SHIFT) \
+ & IOAPIC_DM_MASK;
+ if (info->delivery_mode == IOAPIC_DM_EXTINT) {
+ info->vector = pic_read_irq(isa_pic);
+ } else {
+ info->vector = entry & IOAPIC_VECTOR_MASK;
+ }
+
+ info->addr = APIC_DEFAULT_ADDRESS | \
+ (info->dest_idx << MSI_ADDR_DEST_IDX_SHIFT) | \
+ (info->dest_mode << MSI_ADDR_DEST_MODE_SHIFT);
+ info->data = (info->vector << MSI_DATA_VECTOR_SHIFT) | \
+ (info->trig_mode << MSI_DATA_TRIGGER_SHIFT) | \
+ (info->delivery_mode << MSI_DATA_DELIVERY_MODE_SHIFT);
+}
+
static void ioapic_service(IOAPICCommonState *s)
{
AddressSpace *ioapic_as = PC_MACHINE(qdev_get_machine())->ioapic_as;
- uint32_t addr, data;
+ struct ioapic_entry_info info;
uint8_t i;
- uint8_t trig_mode;
- uint8_t vector;
- uint8_t delivery_mode;
uint32_t mask;
uint64_t entry;
- uint16_t dest_idx;
- uint8_t dest_mode;
for (i = 0; i < IOAPIC_NUM_PINS; i++) {
mask = 1 << i;
@@ -68,33 +106,18 @@ static void ioapic_service(IOAPICCommonState *s)
int coalesce = 0;
entry = s->ioredtbl[i];
- if (!(entry & IOAPIC_LVT_MASKED)) {
- trig_mode = ((entry >> IOAPIC_LVT_TRIGGER_MODE_SHIFT) & 1);
- /*
- * By default, this would be dest_id[8] +
- * reserved[8]. When IR is enabled, this would be
- * interrupt_index[15] + interrupt_format[1]. This
- * field never means anything, but only used to
- * generate corresponding MSI.
- */
- dest_idx = entry >> IOAPIC_LVT_DEST_IDX_SHIFT;
- dest_mode = (entry >> IOAPIC_LVT_DEST_MODE_SHIFT) & 1;
- delivery_mode =
- (entry >> IOAPIC_LVT_DELIV_MODE_SHIFT) & IOAPIC_DM_MASK;
- if (trig_mode == IOAPIC_TRIGGER_EDGE) {
+ ioapic_entry_parse(entry, &info);
+ if (!info.masked) {
+ if (info.trig_mode == IOAPIC_TRIGGER_EDGE) {
s->irr &= ~mask;
} else {
coalesce = s->ioredtbl[i] & IOAPIC_LVT_REMOTE_IRR;
s->ioredtbl[i] |= IOAPIC_LVT_REMOTE_IRR;
}
- if (delivery_mode == IOAPIC_DM_EXTINT) {
- vector = pic_read_irq(isa_pic);
- } else {
- vector = entry & IOAPIC_VECTOR_MASK;
- }
+
#ifdef CONFIG_KVM
if (kvm_irqchip_is_split()) {
- if (trig_mode == IOAPIC_TRIGGER_EDGE) {
+ if (info.trig_mode == IOAPIC_TRIGGER_EDGE) {
kvm_set_irq(kvm_state, i, 1);
kvm_set_irq(kvm_state, i, 0);
} else {
@@ -111,13 +134,7 @@ static void ioapic_service(IOAPICCommonState *s)
* the IOAPIC message into a MSI one, and its
* address space will decide whether we need a
* translation. */
- addr = APIC_DEFAULT_ADDRESS | \
- (dest_idx << MSI_ADDR_DEST_IDX_SHIFT) |
- (dest_mode << MSI_ADDR_DEST_MODE_SHIFT);
- data = (vector << MSI_DATA_VECTOR_SHIFT) |
- (trig_mode << MSI_DATA_TRIGGER_SHIFT) |
- (delivery_mode << MSI_DATA_DELIVERY_MODE_SHIFT);
- stl_le_phys(ioapic_as, addr, data);
+ stl_le_phys(ioapic_as, info.addr, info.data);
}
}
}
@@ -168,30 +185,11 @@ static void ioapic_update_kvm_routes(IOAPICCommonState *s)
if (kvm_irqchip_is_split()) {
for (i = 0; i < IOAPIC_NUM_PINS; i++) {
- uint64_t entry = s->ioredtbl[i];
- uint8_t trig_mode;
- uint8_t delivery_mode;
- uint8_t dest;
- uint8_t dest_mode;
- uint64_t pin_polarity;
MSIMessage msg;
-
- trig_mode = ((entry >> IOAPIC_LVT_TRIGGER_MODE_SHIFT) & 1);
- dest = entry >> IOAPIC_LVT_DEST_SHIFT;
- dest_mode = (entry >> IOAPIC_LVT_DEST_MODE_SHIFT) & 1;
- pin_polarity = (entry >> IOAPIC_LVT_TRIGGER_MODE_SHIFT) & 1;
- delivery_mode =
- (entry >> IOAPIC_LVT_DELIV_MODE_SHIFT) & IOAPIC_DM_MASK;
-
- msg.address = APIC_DEFAULT_ADDRESS;
- msg.address |= dest_mode << 2;
- msg.address |= dest << 12;
-
- msg.data = entry & IOAPIC_VECTOR_MASK;
- msg.data |= delivery_mode << APIC_DELIVERY_MODE_SHIFT;
- msg.data |= pin_polarity << APIC_POLARITY_SHIFT;
- msg.data |= trig_mode << APIC_TRIG_MODE_SHIFT;
-
+ struct ioapic_entry_info info;
+ ioapic_entry_parse(s->ioredtbl[i], &info);
+ msg.address = info.addr;
+ msg.data = info.data;
kvm_irqchip_update_msi_route(kvm_state, i, msg, NULL);
}
kvm_irqchip_commit_routes(kvm_state);
--
2.4.11
next prev parent reply other threads:[~2016-05-05 3:27 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-05-05 3:25 [Qemu-devel] [PATCH v6 00/26] IOMMU: Enable interrupt remapping for Intel IOMMU Peter Xu
2016-05-05 3:25 ` [Qemu-devel] [PATCH v6 01/26] acpi: enable INTR for DMAR report structure Peter Xu
2016-05-05 3:25 ` [Qemu-devel] [PATCH v6 02/26] intel_iommu: allow queued invalidation for IR Peter Xu
2016-05-05 3:25 ` [Qemu-devel] [PATCH v6 03/26] intel_iommu: set IR bit for ECAP register Peter Xu
2016-05-05 3:25 ` [Qemu-devel] [PATCH v6 04/26] acpi: add DMAR scope definition for root IOAPIC Peter Xu
2016-05-05 3:25 ` [Qemu-devel] [PATCH v6 05/26] intel_iommu: define interrupt remap table addr register Peter Xu
2016-05-05 3:25 ` [Qemu-devel] [PATCH v6 06/26] intel_iommu: handle interrupt remap enable Peter Xu
2016-05-05 3:25 ` [Qemu-devel] [PATCH v6 07/26] intel_iommu: define several structs for IOMMU IR Peter Xu
2016-05-05 3:25 ` [Qemu-devel] [PATCH v6 08/26] intel_iommu: provide helper function vtd_get_iommu Peter Xu
2016-05-05 9:29 ` David Kiarie
2016-05-09 6:15 ` Peter Xu
2016-05-05 3:25 ` [Qemu-devel] [PATCH v6 09/26] intel_iommu: add IR translation faults defines Peter Xu
2016-05-05 3:25 ` [Qemu-devel] [PATCH v6 10/26] intel_iommu: Add support for PCI MSI remap Peter Xu
2016-05-05 3:25 ` [Qemu-devel] [PATCH v6 11/26] q35: ioapic: add support for emulated IOAPIC IR Peter Xu
2016-05-05 3:25 ` Peter Xu [this message]
2016-05-05 3:25 ` [Qemu-devel] [PATCH v6 13/26] intel_iommu: add support for split irqchip Peter Xu
2016-05-05 3:25 ` [Qemu-devel] [PATCH v6 14/26] q35: add "intremap" parameter to enable IR Peter Xu
2016-05-05 3:25 ` [Qemu-devel] [PATCH v6 15/26] intel_iommu: introduce IEC notifiers Peter Xu
2016-05-05 3:25 ` [Qemu-devel] [PATCH v6 16/26] ioapic: register VT-d IEC invalidate notifier Peter Xu
2016-05-05 3:25 ` [Qemu-devel] [PATCH v6 17/26] ioapic: keep RO bits for IOAPIC entry Peter Xu
2016-05-05 3:25 ` [Qemu-devel] [PATCH v6 18/26] ioapic: clear remote irr bit for edge-triggered interrupts Peter Xu
2016-05-05 3:25 ` [Qemu-devel] [PATCH v6 19/26] intel_iommu: Add support for Extended Interrupt Mode Peter Xu
2016-05-05 3:25 ` [Qemu-devel] [PATCH v6 20/26] intel_iommu: add SID validation for IR Peter Xu
2016-05-05 3:25 ` [Qemu-devel] [PATCH v6 21/26] x86-iommu: introduce parent class Peter Xu
2016-05-05 3:25 ` [Qemu-devel] [PATCH v6 22/26] x86-iommu: replace existing VT-d hooks into X86 ones Peter Xu
2016-05-05 9:35 ` Jan Kiszka
2016-05-09 5:23 ` Peter Xu
2016-05-05 3:25 ` [Qemu-devel] [PATCH v6 23/26] kvm-irqchip: simplify kvm_irqchip_add_msi_route Peter Xu
2016-05-05 3:25 ` [Qemu-devel] [PATCH v6 24/26] kvm-irqchip: i386: add hook for add/remove virq Peter Xu
2016-05-09 8:02 ` Peter Xu
2016-05-10 8:11 ` Peter Xu
2016-05-05 3:26 ` [Qemu-devel] [PATCH v6 25/26] kvm-irqchip: x86: add msi route notify fn Peter Xu
2016-05-05 3:26 ` [Qemu-devel] [PATCH v6 26/26] kvm-irqchip: do explicit commit when update irq Peter Xu
2016-05-05 4:36 ` [Qemu-devel] [PATCH v6 00/26] IOMMU: Enable interrupt remapping for Intel IOMMU Peter Xu
2016-05-09 17:15 ` Radim Krčmář
2016-05-09 20:37 ` Radim Krčmář
2016-05-10 6:16 ` Peter Xu
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