From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44484) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aymlk-0007kA-U4 for qemu-devel@nongnu.org; Fri, 06 May 2016 16:54:56 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aymlZ-00076Z-4z for qemu-devel@nongnu.org; Fri, 06 May 2016 16:54:35 -0400 Received: from mx1.redhat.com ([209.132.183.28]:57745) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aymlY-00072u-Uo for qemu-devel@nongnu.org; Fri, 06 May 2016 16:54:29 -0400 From: =?UTF-8?q?Radim=20Kr=C4=8Dm=C3=A1=C5=99?= Date: Fri, 6 May 2016 22:53:46 +0200 Message-Id: <1462568028-31037-3-git-send-email-rkrcmar@redhat.com> In-Reply-To: <1462568028-31037-1-git-send-email-rkrcmar@redhat.com> References: <1462568028-31037-1-git-send-email-rkrcmar@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH 2/4] intel_iommu: use deliver_msi APIC callback List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Paolo Bonzini , "Lan, Tianyu" , Igor Mammedov , Jan Kiszka , Peter Xu , Eduardo Habkost , Richard Henderson The memory-mapped interface cannot express x2APIC destinations that are a result of remapping. Signed-off-by: Radim Kr=C4=8Dm=C3=A1=C5=99 --- hw/i386/intel_iommu.c | 29 ++++++++++++++++++----------- 1 file changed, 18 insertions(+), 11 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index bee85e469477..d10064289551 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -26,6 +26,7 @@ #include "hw/pci/pci.h" #include "hw/boards.h" #include "hw/i386/x86-iommu.h" +#include "hw/i386/apic_internal.h" =20 /*#define DEBUG_INTEL_IOMMU*/ #ifdef DEBUG_INTEL_IOMMU @@ -268,24 +269,33 @@ static void vtd_update_iotlb(IntelIOMMUState *s, ui= nt16_t source_id, g_hash_table_replace(s->iotlb, key, entry); } =20 +static void apic_deliver_msi(MSIMessage *msi) +{ + /* Conjure apic-bound msi delivery out of thin air. */ + X86CPU *cpu =3D X86_CPU(first_cpu); + APICCommonState *apic_state =3D APIC_COMMON(cpu->apic_state); + APICCommonClass *apic_class =3D APIC_COMMON_GET_CLASS(apic_state); + + apic_class->deliver_msi(msi); +} + /* Given the reg addr of both the message data and address, generate an * interrupt via MSI. */ static void vtd_generate_interrupt(IntelIOMMUState *s, hwaddr mesg_addr_= reg, hwaddr mesg_data_reg) { - hwaddr addr; - uint32_t data; + MSIMessage msi; =20 assert(mesg_data_reg < DMAR_REG_SIZE); assert(mesg_addr_reg < DMAR_REG_SIZE); =20 - addr =3D vtd_get_long_raw(s, mesg_addr_reg); - data =3D vtd_get_long_raw(s, mesg_data_reg); + msi.address =3D vtd_get_quad_raw(s, mesg_addr_reg); + msi.data =3D vtd_get_long_raw(s, mesg_data_reg); =20 VTD_DPRINTF(FLOG, "msi: addr 0x%"PRIx64 " data 0x%"PRIx32, addr, dat= a); - address_space_stl_le(&address_space_memory, addr, data, - MEMTXATTRS_UNSPECIFIED, NULL); + + apic_deliver_msi(&msi); } =20 /* Generate a fault event to software via MSI if conditions are met. @@ -2113,6 +2123,7 @@ static void vtd_generate_msi_message(VTDIrq *irq, M= SIMessage *msg_out) msg.dest_mode =3D irq->dest_mode; msg.redir_hint =3D irq->redir_hint; msg.dest =3D irq->dest; + msg.__addr_hi =3D irq->dest & 0xffffff00; msg.__addr_head =3D 0xfee; /* Keep this from original MSI address bits */ msg.__not_used =3D irq->msi_addr_last_bits; @@ -2262,11 +2273,7 @@ static MemTxResult vtd_mem_ir_write(void *opaque, = hwaddr addr, VTD_DPRINTF(IR, "delivering MSI 0x%"PRIx64":0x%"PRIx32, to.address, to.data); =20 - if (dma_memory_write(&address_space_memory, to.address, - &to.data, size)) { - VTD_DPRINTF(GENERAL, "error: fail to write 0x%"PRIx64 - " value 0x%"PRIx32, to.address, to.data); - } + apic_deliver_msi(&to); =20 return MEMTX_OK; } --=20 2.8.2