From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44783) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1azsAh-00012h-6A for qemu-devel@nongnu.org; Mon, 09 May 2016 16:53:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1azsAV-00078u-Hm for qemu-devel@nongnu.org; Mon, 09 May 2016 16:52:53 -0400 Received: from mx1.redhat.com ([209.132.183.28]:46788) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1azsAV-00077A-7I for qemu-devel@nongnu.org; Mon, 09 May 2016 16:52:43 -0400 From: =?UTF-8?q?Radim=20Kr=C4=8Dm=C3=A1=C5=99?= Date: Mon, 9 May 2016 22:49:00 +0200 Message-Id: <1462826940-2422-1-git-send-email-rkrcmar@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH] target-i386: implement CPUID[0xB] (Extended Topology Enumeration) List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Richard Henderson , Eduardo Habkost I looked at a dozen Intel CPU that have this CPUID and all of them always had Core offset as 1 (a wasted bit when hyperthreading is disabled) and Package offset at least 4 (wasted bits at <=3D 4 cores). QEMU uses more compact IDs and it doesn't make much sense to change it now. I keep the SMT and Core sub-leaves even if there is just one thread/core; it makes the code simpler and there should be no harm. Signed-off-by: Radim Kr=C4=8Dm=C3=A1=C5=99 --- target-i386/cpu.c | 27 +++++++++++++++++++++++++++ target-i386/cpu.h | 5 +++++ 2 files changed, 32 insertions(+) diff --git a/target-i386/cpu.c b/target-i386/cpu.c index d0b5b691563c..4f8c32cccc88 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -35,6 +35,7 @@ #include "sysemu/arch_init.h" =20 #include "hw/hw.h" +#include "hw/i386/topology.h" #if defined(CONFIG_KVM) #include #endif @@ -2460,6 +2461,32 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t inde= x, uint32_t count, *edx =3D 0; } break; + case 0xB: + /* Extended Topology Enumeration Leaf */ + *ecx =3D count & 0xff; + *edx =3D cpu->apic_id; + + switch (*ecx) { + case 0: + *eax =3D apicid_core_offset(smp_cores, smp_threads); + *ebx =3D smp_threads; + *ecx |=3D CPUID_TOPOLOGY_LEVEL_SMT; + break; + case 1: + *eax =3D apicid_pkg_offset(smp_cores, smp_threads); + *ebx =3D smp_cores * smp_threads; + *ecx |=3D CPUID_TOPOLOGY_LEVEL_CORE; + break; + default: + *eax =3D 0; + *ebx =3D 0; + *ecx |=3D CPUID_TOPOLOGY_LEVEL_INVALID; + } + + /* Preserve reserved bits. Extremely unlikely to make a differe= nce. */ + *eax &=3D 0x1f; + *ebx &=3D 0xffff; + break; case 0xD: { KVMState *s =3D cs->kvm_state; uint64_t ena_mask; diff --git a/target-i386/cpu.h b/target-i386/cpu.h index 732eb6d7ec79..b460c2debc1c 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -635,6 +635,11 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_MWAIT_IBE (1U << 1) /* Interrupts can exit capability = */ #define CPUID_MWAIT_EMX (1U << 0) /* enumeration supported */ =20 +/* CPUID[0xB].ECX level types */ +#define CPUID_TOPOLOGY_LEVEL_INVALID (0U << 8) +#define CPUID_TOPOLOGY_LEVEL_SMT (1U << 8) +#define CPUID_TOPOLOGY_LEVEL_CORE (2U << 8) + #ifndef HYPERV_SPINLOCK_NEVER_RETRY #define HYPERV_SPINLOCK_NEVER_RETRY 0xFFFFFFFF #endif --=20 2.8.2