From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 42/43] hw/arm: QOM'ify strongarm.c
Date: Thu, 12 May 2016 14:33:04 +0100 [thread overview]
Message-ID: <1463059985-2272-43-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1463059985-2272-1-git-send-email-peter.maydell@linaro.org>
From: "xiaoqiang.zhao" <zxq_yx_007@163.com>
Drop the use of old SysBus init function and use instance_init
Signed-off-by: xiaoqiang zhao <zxq_yx_007@163.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/strongarm.c | 66 +++++++++++++++++++++++-------------------------------
1 file changed, 28 insertions(+), 38 deletions(-)
diff --git a/hw/arm/strongarm.c b/hw/arm/strongarm.c
index 1eeb1ab..3bc8a98 100644
--- a/hw/arm/strongarm.c
+++ b/hw/arm/strongarm.c
@@ -179,19 +179,18 @@ static const MemoryRegionOps strongarm_pic_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static int strongarm_pic_initfn(SysBusDevice *sbd)
+static void strongarm_pic_initfn(Object *obj)
{
- DeviceState *dev = DEVICE(sbd);
- StrongARMPICState *s = STRONGARM_PIC(dev);
+ DeviceState *dev = DEVICE(obj);
+ StrongARMPICState *s = STRONGARM_PIC(obj);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
qdev_init_gpio_in(dev, strongarm_pic_set_irq, SA_PIC_SRCS);
- memory_region_init_io(&s->iomem, OBJECT(s), &strongarm_pic_ops, s,
+ memory_region_init_io(&s->iomem, obj, &strongarm_pic_ops, s,
"pic", 0x1000);
sysbus_init_mmio(sbd, &s->iomem);
sysbus_init_irq(sbd, &s->irq);
sysbus_init_irq(sbd, &s->fiq);
-
- return 0;
}
static int strongarm_pic_post_load(void *opaque, int version_id)
@@ -217,9 +216,7 @@ static VMStateDescription vmstate_strongarm_pic_regs = {
static void strongarm_pic_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
- SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
- k->init = strongarm_pic_initfn;
dc->desc = "StrongARM PIC";
dc->vmsd = &vmstate_strongarm_pic_regs;
}
@@ -228,6 +225,7 @@ static const TypeInfo strongarm_pic_info = {
.name = TYPE_STRONGARM_PIC,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(StrongARMPICState),
+ .instance_init = strongarm_pic_initfn,
.class_init = strongarm_pic_class_init,
};
@@ -381,9 +379,10 @@ static const MemoryRegionOps strongarm_rtc_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static int strongarm_rtc_init(SysBusDevice *dev)
+static void strongarm_rtc_init(Object *obj)
{
- StrongARMRTCState *s = STRONGARM_RTC(dev);
+ StrongARMRTCState *s = STRONGARM_RTC(obj);
+ SysBusDevice *dev = SYS_BUS_DEVICE(obj);
struct tm tm;
s->rttr = 0x0;
@@ -400,11 +399,9 @@ static int strongarm_rtc_init(SysBusDevice *dev)
sysbus_init_irq(dev, &s->rtc_irq);
sysbus_init_irq(dev, &s->rtc_hz_irq);
- memory_region_init_io(&s->iomem, OBJECT(s), &strongarm_rtc_ops, s,
+ memory_region_init_io(&s->iomem, obj, &strongarm_rtc_ops, s,
"rtc", 0x10000);
sysbus_init_mmio(dev, &s->iomem);
-
- return 0;
}
static void strongarm_rtc_pre_save(void *opaque)
@@ -443,9 +440,7 @@ static const VMStateDescription vmstate_strongarm_rtc_regs = {
static void strongarm_rtc_sysbus_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
- SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
- k->init = strongarm_rtc_init;
dc->desc = "StrongARM RTC Controller";
dc->vmsd = &vmstate_strongarm_rtc_regs;
}
@@ -454,6 +449,7 @@ static const TypeInfo strongarm_rtc_sysbus_info = {
.name = TYPE_STRONGARM_RTC,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(StrongARMRTCState),
+ .instance_init = strongarm_rtc_init,
.class_init = strongarm_rtc_sysbus_class_init,
};
@@ -646,16 +642,17 @@ static DeviceState *strongarm_gpio_init(hwaddr base,
return dev;
}
-static int strongarm_gpio_initfn(SysBusDevice *sbd)
+static void strongarm_gpio_initfn(Object *obj)
{
- DeviceState *dev = DEVICE(sbd);
- StrongARMGPIOInfo *s = STRONGARM_GPIO(dev);
+ DeviceState *dev = DEVICE(obj);
+ StrongARMGPIOInfo *s = STRONGARM_GPIO(obj);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
int i;
qdev_init_gpio_in(dev, strongarm_gpio_set, 28);
qdev_init_gpio_out(dev, s->handler, 28);
- memory_region_init_io(&s->iomem, OBJECT(s), &strongarm_gpio_ops, s,
+ memory_region_init_io(&s->iomem, obj, &strongarm_gpio_ops, s,
"gpio", 0x1000);
sysbus_init_mmio(sbd, &s->iomem);
@@ -663,8 +660,6 @@ static int strongarm_gpio_initfn(SysBusDevice *sbd)
sysbus_init_irq(sbd, &s->irqs[i]);
}
sysbus_init_irq(sbd, &s->irqX);
-
- return 0;
}
static const VMStateDescription vmstate_strongarm_gpio_regs = {
@@ -687,9 +682,7 @@ static const VMStateDescription vmstate_strongarm_gpio_regs = {
static void strongarm_gpio_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
- SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
- k->init = strongarm_gpio_initfn;
dc->desc = "StrongARM GPIO controller";
dc->vmsd = &vmstate_strongarm_gpio_regs;
}
@@ -698,6 +691,7 @@ static const TypeInfo strongarm_gpio_info = {
.name = TYPE_STRONGARM_GPIO,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(StrongARMGPIOInfo),
+ .instance_init = strongarm_gpio_initfn,
.class_init = strongarm_gpio_class_init,
};
@@ -824,20 +818,19 @@ static const MemoryRegionOps strongarm_ppc_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static int strongarm_ppc_init(SysBusDevice *sbd)
+static void strongarm_ppc_init(Object *obj)
{
- DeviceState *dev = DEVICE(sbd);
- StrongARMPPCInfo *s = STRONGARM_PPC(dev);
+ DeviceState *dev = DEVICE(obj);
+ StrongARMPPCInfo *s = STRONGARM_PPC(obj);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
qdev_init_gpio_in(dev, strongarm_ppc_set, 22);
qdev_init_gpio_out(dev, s->handler, 22);
- memory_region_init_io(&s->iomem, OBJECT(s), &strongarm_ppc_ops, s,
+ memory_region_init_io(&s->iomem, obj, &strongarm_ppc_ops, s,
"ppc", 0x1000);
sysbus_init_mmio(sbd, &s->iomem);
-
- return 0;
}
static const VMStateDescription vmstate_strongarm_ppc_regs = {
@@ -859,9 +852,7 @@ static const VMStateDescription vmstate_strongarm_ppc_regs = {
static void strongarm_ppc_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
- SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
- k->init = strongarm_ppc_init;
dc->desc = "StrongARM PPC controller";
dc->vmsd = &vmstate_strongarm_ppc_regs;
}
@@ -870,6 +861,7 @@ static const TypeInfo strongarm_ppc_info = {
.name = TYPE_STRONGARM_PPC,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(StrongARMPPCInfo),
+ .instance_init = strongarm_ppc_init,
.class_init = strongarm_ppc_class_init,
};
@@ -1231,11 +1223,12 @@ static const MemoryRegionOps strongarm_uart_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static int strongarm_uart_init(SysBusDevice *dev)
+static void strongarm_uart_init(Object *obj)
{
- StrongARMUARTState *s = STRONGARM_UART(dev);
+ StrongARMUARTState *s = STRONGARM_UART(obj);
+ SysBusDevice *dev = SYS_BUS_DEVICE(obj);
- memory_region_init_io(&s->iomem, OBJECT(s), &strongarm_uart_ops, s,
+ memory_region_init_io(&s->iomem, obj, &strongarm_uart_ops, s,
"uart", 0x10000);
sysbus_init_mmio(dev, &s->iomem);
sysbus_init_irq(dev, &s->irq);
@@ -1250,8 +1243,6 @@ static int strongarm_uart_init(SysBusDevice *dev)
strongarm_uart_event,
s);
}
-
- return 0;
}
static void strongarm_uart_reset(DeviceState *dev)
@@ -1321,9 +1312,7 @@ static Property strongarm_uart_properties[] = {
static void strongarm_uart_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
- SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
- k->init = strongarm_uart_init;
dc->desc = "StrongARM UART controller";
dc->reset = strongarm_uart_reset;
dc->vmsd = &vmstate_strongarm_uart_regs;
@@ -1334,6 +1323,7 @@ static const TypeInfo strongarm_uart_info = {
.name = TYPE_STRONGARM_UART,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(StrongARMUARTState),
+ .instance_init = strongarm_uart_init,
.class_init = strongarm_uart_class_init,
};
--
1.9.1
next prev parent reply other threads:[~2016-05-12 13:33 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-05-12 13:32 [Qemu-devel] [PULL 00/43] target-arm queue Peter Maydell
2016-05-12 13:32 ` [Qemu-devel] [PULL 01/43] blizzard: Remove support for DEPTH != 32 Peter Maydell
2016-05-12 13:32 ` [Qemu-devel] [PULL 02/43] omap_lcdc: " Peter Maydell
2016-05-12 13:32 ` [Qemu-devel] [PULL 03/43] hw/intc: QOM'ify etraxfs_pic.c Peter Maydell
2016-05-12 13:32 ` [Qemu-devel] [PULL 04/43] hw/intc: QOM'ify exynos4210_combiner.c Peter Maydell
2016-05-12 13:32 ` [Qemu-devel] [PULL 05/43] hw/intc: QOM'ify exynos4210_gic.c Peter Maydell
2016-05-12 13:32 ` [Qemu-devel] [PULL 06/43] hw/intc: QOM'ify imx_avic.c Peter Maydell
2016-05-12 13:32 ` [Qemu-devel] [PULL 07/43] hw/intc: QOM'ify pl190.c Peter Maydell
2016-05-12 13:32 ` [Qemu-devel] [PULL 08/43] hw/intc: QOM'ify slavio_intctl.c Peter Maydell
2016-05-12 13:32 ` [Qemu-devel] [PULL 09/43] hw/intc: QOM'ify grlib_irqmp.c Peter Maydell
2016-05-12 13:32 ` [Qemu-devel] [PULL 10/43] hw/intc: QOM'ify omap_intc.c Peter Maydell
2016-05-12 13:32 ` [Qemu-devel] [PULL 11/43] bcm2835_property: use cached values when querying framebuffer Peter Maydell
2016-05-12 13:32 ` [Qemu-devel] [PULL 12/43] hw/arm/nseries: Allocating Large sized arrays to heap Peter Maydell
2016-05-12 13:32 ` [Qemu-devel] [PULL 13/43] target-arm: Stage 2 permission fault was fixed in AArch32 state Peter Maydell
2016-05-12 13:32 ` [Qemu-devel] [PULL 14/43] target-arm: Fix descriptor address masking in ARM address translation Peter Maydell
2016-05-12 13:32 ` [Qemu-devel] [PULL 15/43] tcg: Add tcg_set_insn_param Peter Maydell
2016-05-12 13:32 ` [Qemu-devel] [PULL 16/43] gen-icount: Use tcg_set_insn_param Peter Maydell
2016-05-12 13:32 ` [Qemu-devel] [PULL 17/43] target-arm: Split data abort syndrome generator Peter Maydell
2016-05-12 13:32 ` [Qemu-devel] [PULL 18/43] target-arm/translate-a64.c: Use extract32 in disas_ldst_reg_imm9 Peter Maydell
2016-05-12 13:32 ` [Qemu-devel] [PULL 19/43] target-arm/translate-a64.c: Unify some of the ldst_reg decoding Peter Maydell
2016-05-12 13:32 ` [Qemu-devel] [PULL 20/43] hw/display: QOM'ify exynos4210_fimd.c Peter Maydell
2016-05-12 13:32 ` [Qemu-devel] [PULL 21/43] ARM: Virt: Set numa-node-id for cpu and memory nodes Peter Maydell
2016-05-12 13:32 ` [Qemu-devel] [PULL 22/43] ACPI: Add GICC Affinity Structure Peter Maydell
2016-05-12 13:32 ` [Qemu-devel] [PULL 23/43] ACPI: Fix the definition of proximity in AcpiSratMemoryAffinity Peter Maydell
2016-05-12 13:32 ` [Qemu-devel] [PULL 24/43] ACPI: move acpi_build_srat_memory to common place Peter Maydell
2016-05-12 13:32 ` [Qemu-devel] [PULL 25/43] ACPI: Virt: Generate SRAT table Peter Maydell
2016-05-12 13:32 ` [Qemu-devel] [PULL 26/43] ARM: Factor out ARM on/off PSCI control functions Peter Maydell
2016-05-12 13:32 ` [Qemu-devel] [PULL 27/43] i.MX: Add i.MX6 System Reset Controller device Peter Maydell
2016-05-12 13:32 ` [Qemu-devel] [PULL 28/43] FIFO: Add a FIFO32 implementation Peter Maydell
2016-05-12 13:32 ` [Qemu-devel] [PULL 29/43] i.MX: Add the Freescale SPI Controller Peter Maydell
2016-05-12 13:32 ` [Qemu-devel] [PULL 30/43] i.MX: Add i.MX6 SOC implementation Peter Maydell
2016-05-12 13:32 ` [Qemu-devel] [PULL 31/43] i.MX: Add sabrelite i.MX6 emulation Peter Maydell
2016-05-12 13:32 ` [Qemu-devel] [PULL 32/43] hw/display/blizzard: Expand out macros Peter Maydell
2016-05-12 13:32 ` [Qemu-devel] [PULL 33/43] hw/display/blizzard: Remove blizzard_template.h Peter Maydell
2016-05-12 13:32 ` [Qemu-devel] [PULL 34/43] target-arm: Avoid unnecessary TLB flush on TCR_EL2, TCR_EL3 writes Peter Maydell
2016-05-12 13:32 ` [Qemu-devel] [PULL 35/43] hw/arm: QOM'ify armv7m.c Peter Maydell
2016-05-12 13:32 ` [Qemu-devel] [PULL 36/43] hw/arm: QOM'ify highbank.c Peter Maydell
2016-05-12 13:32 ` [Qemu-devel] [PULL 37/43] hw/arm: QOM'ify integratorcp.c Peter Maydell
2016-05-12 13:33 ` [Qemu-devel] [PULL 38/43] hw/arm: QOM'ify pxa2xx.c Peter Maydell
2016-05-12 13:33 ` [Qemu-devel] [PULL 39/43] hw/arm: QOM'ify pxa2xx_pic.c Peter Maydell
2016-05-12 13:33 ` [Qemu-devel] [PULL 40/43] hw/arm: QOM'ify spitz.c Peter Maydell
2016-05-12 13:33 ` [Qemu-devel] [PULL 41/43] hw/arm: QOM'ify stellaris.c Peter Maydell
2016-05-12 13:33 ` Peter Maydell [this message]
2016-05-12 13:33 ` [Qemu-devel] [PULL 43/43] hw/arm: QOM'ify versatilepb.c Peter Maydell
2016-05-12 15:33 ` [Qemu-devel] [PULL 00/43] target-arm queue Peter Maydell
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