From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57717) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b2KZn-00020p-Uu for qemu-devel@nongnu.org; Mon, 16 May 2016 11:37:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1b2KZd-0006cA-Rz for qemu-devel@nongnu.org; Mon, 16 May 2016 11:36:58 -0400 Received: from mail-wm0-x241.google.com ([2a00:1450:400c:c09::241]:32846) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b2KZd-0006c4-M0 for qemu-devel@nongnu.org; Mon, 16 May 2016 11:36:49 -0400 Received: by mail-wm0-x241.google.com with SMTP id r12so18962631wme.0 for ; Mon, 16 May 2016 08:36:49 -0700 (PDT) Received: from 640k.lan (dynamic-adsl-78-12-252-58.clienti.tiscali.it. [78.12.252.58]) by smtp.gmail.com with ESMTPSA id lf9sm34386875wjc.44.2016.05.16.08.36.48 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 16 May 2016 08:36:48 -0700 (PDT) Sender: Paolo Bonzini From: Paolo Bonzini Date: Mon, 16 May 2016 17:35:53 +0200 Message-Id: <1463412982-6681-22-git-send-email-pbonzini@redhat.com> In-Reply-To: <1463412982-6681-1-git-send-email-pbonzini@redhat.com> References: <1463412982-6681-1-git-send-email-pbonzini@redhat.com> Subject: [Qemu-devel] [PATCH 21/50] arm: include cpu-qom.h in files that require ARMCPU List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org This will keep things working when cpu.h will not be included indirectly almost everywhere (either directly or through qemu-common.h). Signed-off-by: Paolo Bonzini --- hw/arm/stm32f205_soc.c | 1 - hw/arm/strongarm.h | 1 + include/hw/arm/arm.h | 2 +- include/hw/arm/exynos4210.h | 1 + include/hw/arm/omap.h | 1 + include/hw/arm/pxa.h | 1 + 6 files changed, 5 insertions(+), 2 deletions(-) diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c index a5ea1e2..9c1dafb 100644 --- a/hw/arm/stm32f205_soc.c +++ b/hw/arm/stm32f205_soc.c @@ -25,7 +25,6 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "qemu-common.h" -#include "cpu.h" #include "hw/arm/arm.h" #include "exec/address-spaces.h" #include "hw/arm/stm32f205_soc.h" diff --git a/hw/arm/strongarm.h b/hw/arm/strongarm.h index 2893f94..cd32bbd 100644 --- a/hw/arm/strongarm.h +++ b/hw/arm/strongarm.h @@ -2,6 +2,7 @@ #define _STRONGARM_H #include "exec/memory.h" +#include "target-arm/cpu-qom.h" #define SA_CS0 0x00000000 #define SA_CS1 0x08000000 diff --git a/include/hw/arm/arm.h b/include/hw/arm/arm.h index b2517f9..8b49a98 100644 --- a/include/hw/arm/arm.h +++ b/include/hw/arm/arm.h @@ -12,9 +12,9 @@ #define ARM_MISC_H 1 #include "exec/memory.h" +#include "target-arm/cpu-qom.h" #include "hw/irq.h" #include "qemu/notify.h" -#include "cpu.h" typedef enum { ARM_ENDIANNESS_UNKNOWN = 0, diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h index 5c1820f..b6d929d 100644 --- a/include/hw/arm/exynos4210.h +++ b/include/hw/arm/exynos4210.h @@ -28,6 +28,7 @@ #include "qemu-common.h" #include "exec/memory.h" +#include "target-arm/cpu-qom.h" #define EXYNOS4210_NCPUS 2 diff --git a/include/hw/arm/omap.h b/include/hw/arm/omap.h index 0ad5fb8..f026c8d 100644 --- a/include/hw/arm/omap.h +++ b/include/hw/arm/omap.h @@ -20,6 +20,7 @@ #include "exec/memory.h" # define hw_omap_h "omap.h" #include "hw/irq.h" +#include "target-arm/cpu-qom.h" # define OMAP_EMIFS_BASE 0x00000000 # define OMAP2_Q0_BASE 0x00000000 diff --git a/include/hw/arm/pxa.h b/include/hw/arm/pxa.h index 259b852..074feac 100644 --- a/include/hw/arm/pxa.h +++ b/include/hw/arm/pxa.h @@ -10,6 +10,7 @@ # define PXA_H "pxa.h" #include "exec/memory.h" +#include "target-arm/cpu-qom.h" /* Interrupt numbers */ # define PXA2XX_PIC_SSP3 0 -- 1.8.3.1