From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49506) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b2e2z-0003UB-P1 for qemu-devel@nongnu.org; Tue, 17 May 2016 08:24:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1b2e2y-0005fs-NB for qemu-devel@nongnu.org; Tue, 17 May 2016 08:24:25 -0400 From: Peter Maydell Date: Tue, 17 May 2016 13:14:16 +0100 Message-Id: <1463487258-27468-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH 0/2] target-arm: ESR IL bit fixes List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org, "Edgar E. Iglesias" , Laurent Desnogues These patches fix some problems with setting the IL bit in ESR syndrome register values: * we were not setting IL for insn abort, watchpoint or swstep (which should all always have IL==1) * we were trying to set the IL bit in arm_cpu_do_interrupt_aarch64() if doing a 32->64 bit exception entry, which was wrong in several ways; instead we should just rely on exception.syndrome already having the correct IL bit value The patches are intended to apply on top of target-arm.next: https://git.linaro.org/people/peter.maydell/qemu-arm.git target-arm.next (which has Edgar's patch which gets us correct IL bit values for data abort exceptions). Peter Maydell (2): target-arm: Set IL bit in syndromes for insn abort, watchpoint, swstep target-arm: Don't try to set ESR IL bit in arm_cpu_do_interrupt_aarch64() target-arm/helper.c | 3 --- target-arm/internals.h | 6 +++--- 2 files changed, 3 insertions(+), 6 deletions(-) -- 1.9.1