From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53260) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b3k7f-0002F3-KU for qemu-devel@nongnu.org; Fri, 20 May 2016 09:05:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1b3k7Z-0004SO-KZ for qemu-devel@nongnu.org; Fri, 20 May 2016 09:05:46 -0400 Received: from smtp2-g21.free.fr ([212.27.42.2]:58827) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b3k7Z-0004Pi-Ba for qemu-devel@nongnu.org; Fri, 20 May 2016 09:05:41 -0400 From: =?UTF-8?q?Herv=C3=A9=20Poussineau?= Date: Fri, 20 May 2016 15:05:03 +0200 Message-Id: <1463749503-27374-1-git-send-email-hpoussin@reactos.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH] gt64xxx: access right I/O port when activating byte swapping List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Leon Alrae , =?UTF-8?q?Herv=C3=A9=20Poussineau?= Incidentally, this fixes YAMON on big endian guest. Signed-off-by: Herv=C3=A9 Poussineau --- hw/mips/gt64xxx_pci.c | 62 +++++++++++++++++++++++++++++++++++++++++++++= ++++-- 1 file changed, 60 insertions(+), 2 deletions(-) diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c index 3f4523d..c76ee88 100644 --- a/hw/mips/gt64xxx_pci.c +++ b/hw/mips/gt64xxx_pci.c @@ -177,6 +177,7 @@ =20 /* PCI Internal */ #define GT_PCI0_CMD (0xc00 >> 2) +#define GT_CMD_MWORDSWAP (1 << 10) #define GT_PCI0_TOR (0xc04 >> 2) #define GT_PCI0_BS_SCS10 (0xc08 >> 2) #define GT_PCI0_BS_SCS32 (0xc0c >> 2) @@ -294,6 +295,62 @@ static void gt64120_isd_mapping(GT64120State *s) memory_region_add_subregion(get_system_memory(), s->ISD_start, &s->I= SD_mem); } =20 +static uint64_t gt64120_pci_io_read(void *opaque, hwaddr addr, + unsigned int size) +{ + GT64120State *s =3D opaque; + uint8_t buf[4]; + + if (s->regs[GT_PCI0_CMD] & GT_CMD_MWORDSWAP) { + addr =3D (addr & ~3) + 4 - size - (addr & 3); + } + + address_space_read(&address_space_io, addr, MEMTXATTRS_UNSPECIFIED, + buf, size); + + if (size =3D=3D 1) { + return buf[0]; + } else if (size =3D=3D 2) { + return lduw_le_p(buf); + } else if (size =3D=3D 4) { + return ldl_le_p(buf); + } else { + g_assert_not_reached(); + } +} + +static void gt64120_pci_io_write(void *opaque, hwaddr addr, uint64_t dat= a, + unsigned int size) +{ + GT64120State *s =3D opaque; + uint8_t buf[4]; + + if (s->regs[GT_PCI0_CMD] & GT_CMD_MWORDSWAP) { + addr =3D (addr & ~3) + 4 - size - (addr & 3); + } + + if (size =3D=3D 1) { + buf[0] =3D data; + } else if (size =3D=3D 2) { + stw_le_p(buf, data); + } else if (size =3D=3D 4) { + stl_le_p(buf, data); + } else { + g_assert_not_reached(); + } + + address_space_write(&address_space_io, addr, MEMTXATTRS_UNSPECIFIED, + buf, size); +} + +static const MemoryRegionOps gt64120_pci_io_ops =3D { + .read =3D gt64120_pci_io_read, + .write =3D gt64120_pci_io_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .impl.max_access_size =3D 4, + .valid.unaligned =3D true, +}; + static void gt64120_pci_mapping(GT64120State *s) { /* Update PCI0IO mapping */ @@ -308,8 +365,9 @@ static void gt64120_pci_mapping(GT64120State *s) s->PCI0IO_length =3D ((s->regs[GT_PCI0IOHD] + 1) - (s->regs[GT_PCI0IOLD] & 0x7f)) << 21; if (s->PCI0IO_length) { - memory_region_init_alias(&s->PCI0IO_mem, OBJECT(s), "pci0-io= ", - get_system_io(), 0, s->PCI0IO_lengt= h); + memory_region_init_io(&s->PCI0IO_mem, OBJECT(s), + >64120_pci_io_ops, + s, "pci0-io", s->PCI0IO_length); memory_region_add_subregion(get_system_memory(), s->PCI0IO_s= tart, &s->PCI0IO_mem); } --=20 2.1.4