From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37516) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b4rUm-0002BM-93 for qemu-devel@nongnu.org; Mon, 23 May 2016 11:10:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1b4rUg-00043D-3s for qemu-devel@nongnu.org; Mon, 23 May 2016 11:10:16 -0400 Received: from mail-wm0-x242.google.com ([2a00:1450:400c:c09::242]:36060) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b4rUf-00042b-PO for qemu-devel@nongnu.org; Mon, 23 May 2016 11:10:10 -0400 Received: by mail-wm0-x242.google.com with SMTP id q62so16004059wmg.3 for ; Mon, 23 May 2016 08:10:09 -0700 (PDT) Sender: Paolo Bonzini From: Paolo Bonzini Date: Mon, 23 May 2016 17:09:41 +0200 Message-Id: <1464016199-43768-7-git-send-email-pbonzini@redhat.com> In-Reply-To: <1464016199-43768-1-git-send-email-pbonzini@redhat.com> References: <1464016199-43768-1-git-send-email-pbonzini@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [Qemu-devel] [PULL 06/24] ioapic: keep RO bits for IOAPIC entry List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Xu From: Peter Xu Currently IOAPIC RO bits can be written. To be better aligned with hardware, we should let them read-only. Reviewed-by: Radim Krčmář Signed-off-by: Peter Xu Message-Id: <1462875682-1349-2-git-send-email-peterx@redhat.com> Signed-off-by: Paolo Bonzini --- hw/intc/ioapic.c | 4 ++++ include/hw/i386/ioapic_internal.h | 5 +++++ 2 files changed, 9 insertions(+) diff --git a/hw/intc/ioapic.c b/hw/intc/ioapic.c index 4f42b91..c27ee83 100644 --- a/hw/intc/ioapic.c +++ b/hw/intc/ioapic.c @@ -281,6 +281,7 @@ ioapic_mem_write(void *opaque, hwaddr addr, uint64_t val, default: index = (s->ioregsel - IOAPIC_REG_REDTBL_BASE) >> 1; if (index >= 0 && index < IOAPIC_NUM_PINS) { + uint64_t ro_bits = s->ioredtbl[index] & IOAPIC_RO_BITS; if (s->ioregsel & 1) { s->ioredtbl[index] &= 0xffffffff; s->ioredtbl[index] |= (uint64_t)val << 32; @@ -288,6 +289,9 @@ ioapic_mem_write(void *opaque, hwaddr addr, uint64_t val, s->ioredtbl[index] &= ~0xffffffffULL; s->ioredtbl[index] |= val; } + /* restore RO bits */ + s->ioredtbl[index] &= IOAPIC_RW_BITS; + s->ioredtbl[index] |= ro_bits; ioapic_service(s); } } diff --git a/include/hw/i386/ioapic_internal.h b/include/hw/i386/ioapic_internal.h index 797ed47..cab9e67 100644 --- a/include/hw/i386/ioapic_internal.h +++ b/include/hw/i386/ioapic_internal.h @@ -47,6 +47,11 @@ #define IOAPIC_LVT_DEST_MODE (1 << IOAPIC_LVT_DEST_MODE_SHIFT) #define IOAPIC_LVT_DELIV_MODE (7 << IOAPIC_LVT_DELIV_MODE_SHIFT) +/* Bits that are read-only for IOAPIC entry */ +#define IOAPIC_RO_BITS (IOAPIC_LVT_REMOTE_IRR | \ + IOAPIC_LVT_DELIV_STATUS) +#define IOAPIC_RW_BITS (~(uint64_t)IOAPIC_RO_BITS) + #define IOAPIC_TRIGGER_EDGE 0 #define IOAPIC_TRIGGER_LEVEL 1 -- 1.8.3.1