From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40642) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b669B-0000CI-KU for qemu-devel@nongnu.org; Thu, 26 May 2016 21:01:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1b669A-0004DX-7w for qemu-devel@nongnu.org; Thu, 26 May 2016 21:01:05 -0400 Received: from mail-qk0-x243.google.com ([2607:f8b0:400d:c09::243]:32944) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b669A-0004DM-3m for qemu-devel@nongnu.org; Thu, 26 May 2016 21:01:04 -0400 Received: by mail-qk0-x243.google.com with SMTP id q184so11240002qkf.0 for ; Thu, 26 May 2016 18:01:03 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Thu, 26 May 2016 18:00:12 -0700 Message-Id: <1464310815-13554-10-git-send-email-rth@twiddle.net> In-Reply-To: <1464310815-13554-1-git-send-email-rth@twiddle.net> References: <1464310815-13554-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH v2 09/12] tcg/sparc: Add support for fence List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: bobby.prani@gmail.com, Blue Swirl Cc: Blue Swirl Signed-off-by: Richard Henderson --- tcg/sparc/tcg-target.inc.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/tcg/sparc/tcg-target.inc.c b/tcg/sparc/tcg-target.inc.c index 9938a50..16d8d8f 100644 --- a/tcg/sparc/tcg-target.inc.c +++ b/tcg/sparc/tcg-target.inc.c @@ -249,6 +249,8 @@ static const int tcg_target_call_oarg_regs[] = { #define STWA (INSN_OP(3) | INSN_OP3(0x14)) #define STXA (INSN_OP(3) | INSN_OP3(0x1e)) +#define MEMBAR (INSN_OP(2) | INSN_OP3(0x28) | INSN_RS1(15) | (1 << 13)) + #ifndef ASI_PRIMARY_LITTLE #define ASI_PRIMARY_LITTLE 0x88 #endif @@ -1450,6 +1452,11 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_arithc(s, a0, TCG_REG_G0, a1, const_args[1], c); break; + case INDEX_op_fence: + /* membar #LoadLoad|#LoadStore|#StoreStore|#StoreLoad */ + tcg_out32(s, MEMBAR | 15); + break; + case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_mov_i64: case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ @@ -1551,6 +1558,7 @@ static const TCGTargetOpDef sparc_op_defs[] = { { INDEX_op_qemu_st_i32, { "sZ", "A" } }, { INDEX_op_qemu_st_i64, { "SZ", "A" } }, + { INDEX_op_fence, { } }, { -1 }, }; -- 2.5.5