From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40319) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b6693-0008Va-B9 for qemu-devel@nongnu.org; Thu, 26 May 2016 21:00:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1b6691-0004Aj-Fm for qemu-devel@nongnu.org; Thu, 26 May 2016 21:00:56 -0400 Received: from mail-qk0-x243.google.com ([2607:f8b0:400d:c09::243]:34833) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b6691-0004Af-Bd for qemu-devel@nongnu.org; Thu, 26 May 2016 21:00:55 -0400 Received: by mail-qk0-x243.google.com with SMTP id z80so3423582qkb.2 for ; Thu, 26 May 2016 18:00:55 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Thu, 26 May 2016 18:00:07 -0700 Message-Id: <1464310815-13554-5-git-send-email-rth@twiddle.net> In-Reply-To: <1464310815-13554-1-git-send-email-rth@twiddle.net> References: <1464310815-13554-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH v2 04/12] tcg/arm: Add support for fence List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: bobby.prani@gmail.com, Andrzej Zaborowski , Peter Maydell Cc: Andrzej Zaborowski Cc: Peter Maydell Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.inc.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c index f9f54c6..951d110 100644 --- a/tcg/arm/tcg-target.inc.c +++ b/tcg/arm/tcg-target.inc.c @@ -313,6 +313,10 @@ typedef enum { INSN_LDRD_REG = 0x000000d0, INSN_STRD_IMM = 0x004000f0, INSN_STRD_REG = 0x000000f0, + + INSN_DMB_ISH = 0x5bf07ff5, + INSN_DMB_MCR = 0xba0f07ee, + } ARMInsn; #define SHIFT_IMM_LSL(im) (((im) << 7) | 0x00) @@ -1923,6 +1927,13 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_udiv(s, COND_AL, args[0], args[1], args[2]); break; + case INDEX_op_fence: + if (use_armv7_instructions) { + tcg_out32(s, INSN_DMB_ISH); + } else if (use_armv6_instructions) { + tcg_out32(s, INSN_DMB_MCR); + } + break; case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ case INDEX_op_call: /* Always emitted via tcg_out_call. */ @@ -1997,6 +2008,7 @@ static const TCGTargetOpDef arm_op_defs[] = { { INDEX_op_div_i32, { "r", "r", "r" } }, { INDEX_op_divu_i32, { "r", "r", "r" } }, + { INDEX_op_fence, { } }, { -1 }, }; -- 2.5.5