From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40372) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b6694-0008WO-ST for qemu-devel@nongnu.org; Thu, 26 May 2016 21:01:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1b6692-0004BC-S6 for qemu-devel@nongnu.org; Thu, 26 May 2016 21:00:57 -0400 Received: from mail-qk0-x241.google.com ([2607:f8b0:400d:c09::241]:34835) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b6692-0004B7-O7 for qemu-devel@nongnu.org; Thu, 26 May 2016 21:00:56 -0400 Received: by mail-qk0-x241.google.com with SMTP id z80so3423615qkb.2 for ; Thu, 26 May 2016 18:00:56 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Thu, 26 May 2016 18:00:08 -0700 Message-Id: <1464310815-13554-6-git-send-email-rth@twiddle.net> In-Reply-To: <1464310815-13554-1-git-send-email-rth@twiddle.net> References: <1464310815-13554-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH v2 05/12] tcg/ia64: Add support for fence List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: bobby.prani@gmail.com, Aurelien Jarno Cc: Aurelien Jarno Signed-off-by: Richard Henderson --- tcg/ia64/tcg-target.inc.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/tcg/ia64/tcg-target.inc.c b/tcg/ia64/tcg-target.inc.c index 395223e..6bbc6dc5 100644 --- a/tcg/ia64/tcg-target.inc.c +++ b/tcg/ia64/tcg-target.inc.c @@ -247,6 +247,7 @@ enum { OPC_LD4_M3 = 0x0a080000000ull, OPC_LD8_M1 = 0x080c0000000ull, OPC_LD8_M3 = 0x0a0c0000000ull, + OPC_MF_M24 = 0x00110000000ull, OPC_MUX1_I3 = 0x0eca0000000ull, OPC_NOP_B9 = 0x04008000000ull, OPC_NOP_F16 = 0x00008000000ull, @@ -2213,6 +2214,9 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_qemu_st(s, args); break; + case INDEX_op_fence: + tcg_out_bundle(s, mmI, OPC_MF_M24, INSN_NOP_M, INSN_NOP_I); + break; case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_mov_i64: case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ @@ -2326,6 +2330,7 @@ static const TCGTargetOpDef ia64_op_defs[] = { { INDEX_op_qemu_st_i32, { "SZ", "r" } }, { INDEX_op_qemu_st_i64, { "SZ", "r" } }, + { INDEX_op_fence, { } }, { -1 }, }; -- 2.5.5