From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33212) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b79gR-0005hS-7l for qemu-devel@nongnu.org; Sun, 29 May 2016 18:59:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1b79gK-0004Tm-Vz for qemu-devel@nongnu.org; Sun, 29 May 2016 18:59:46 -0400 Received: from mail.uni-paderborn.de ([131.234.142.9]:38722) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b79gK-0004TV-L2 for qemu-devel@nongnu.org; Sun, 29 May 2016 18:59:40 -0400 Received: from wormulon.uni-paderborn.de ([131.234.189.22] helo=localhost.localdomain) by mail.uni-paderborn.de with esmtp (Exim 4.84_2 nylar) id 1b79gH-0001Rd-NB for qemu-devel@nongnu.org; Mon, 30 May 2016 00:59:37 +0200 Received: from mail.uni-paderborn.de by wormulon with queue id 1137698-5 for qemu-devel@nongnu.org; Sun, 29 May 2016 22:59:36 GMT From: peer.adelt@c-lab.de Date: Mon, 30 May 2016 00:59:26 +0200 Message-Id: <1464562768-8954-3-git-send-email-peer.adelt@c-lab.de> In-Reply-To: <1464562768-8954-1-git-send-email-peer.adelt@c-lab.de> References: <1464562768-8954-1-git-send-email-peer.adelt@c-lab.de> Subject: [Qemu-devel] [PATCH 2/4] target-tricore: Added MADD.F and MSUB.F instructions List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: kbastian@mail.uni-paderborn.de, Peer Adelt From: Peer Adelt Multiplies D[a] and D[b] and adds/subtracts the result to/from D[d]. The result is put in D[c]. All operands are floating-point numbers. Signed-off-by: Peer Adelt --- target-tricore/fpu_helper.c | 54 +++++++++++++++++++++++++++++++++++++++++++++ target-tricore/helper.h | 2 ++ target-tricore/translate.c | 8 +++++++ 3 files changed, 64 insertions(+) diff --git a/target-tricore/fpu_helper.c b/target-tricore/fpu_helper.c index ccaa6b0..3207818 100644 --- a/target-tricore/fpu_helper.c +++ b/target-tricore/fpu_helper.c @@ -159,6 +159,60 @@ uint32_t helper_fdiv(CPUTriCoreState *env, uint32_t r1, uint32_t r2) return (uint32_t)f_result; } +uint32_t helper_fmadd(CPUTriCoreState *env, uint32_t r1, + uint32_t r2, uint32_t r3) +{ + uint32_t flags; + float32 arg1 = make_float32(r1); + float32 arg2 = make_float32(r2); + float32 arg3 = make_float32(r3); + float32 f_result; + + flags = f_get_excp_flags(env); + f_result = float32_muladd(arg1, arg2, arg3, flags, &env->fp_status); + + if (flags) { + /* If the output is a NaN, but the inputs aren't, + we return a unique value. */ + if ((flags & float_flag_invalid) + && !float32_is_any_nan(arg1) + && !float32_is_any_nan(arg2)) { + f_result = MUL_NAN; + } + f_update_psw_flags(env, flags); + } else { + env->FPU_FS = 0; + } + return (uint32_t)f_result; +} + +uint32_t helper_fmsub(CPUTriCoreState *env, uint32_t r1, + uint32_t r2, uint32_t r3) +{ + uint32_t flags; + float32 arg1 = make_float32(r1); + float32 arg2 = make_float32(r2); + float32 arg3 = make_float32(r3); + float32 f_result; + + flags = f_get_excp_flags(env); + f_result = float32_muladd(-arg1, arg2, arg3, flags, &env->fp_status); + + if (flags) { + /* If the output is a NaN, but the inputs aren't, + we return a unique value. */ + if ((flags & float_flag_invalid) + && !float32_is_any_nan(arg1) + && !float32_is_any_nan(arg2)) { + f_result = MUL_NAN; + } + f_update_psw_flags(env, flags); + } else { + env->FPU_FS = 0; + } + return (uint32_t)f_result; +} + uint32_t helper_fcmp(CPUTriCoreState *env, uint32_t r1, uint32_t r2) { uint32_t result, flags; diff --git a/target-tricore/helper.h b/target-tricore/helper.h index 467c880..c897a44 100644 --- a/target-tricore/helper.h +++ b/target-tricore/helper.h @@ -109,6 +109,8 @@ DEF_HELPER_3(fadd, i32, env, i32, i32) DEF_HELPER_3(fsub, i32, env, i32, i32) DEF_HELPER_3(fmul, i32, env, i32, i32) DEF_HELPER_3(fdiv, i32, env, i32, i32) +DEF_HELPER_4(fmadd, i32, env, i32, i32, i32) +DEF_HELPER_4(fmsub, i32, env, i32, i32, i32) DEF_HELPER_3(fcmp, i32, env, i32, i32) DEF_HELPER_2(ftoi, i32, env, i32) DEF_HELPER_2(itof, i32, env, i32) diff --git a/target-tricore/translate.c b/target-tricore/translate.c index a109c15..e66b433 100644 --- a/target-tricore/translate.c +++ b/target-tricore/translate.c @@ -7096,6 +7096,14 @@ static void decode_rrr_divide(CPUTriCoreState *env, DisasContext *ctx) case OPC2_32_RRR_SUB_F: gen_helper_fsub(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r3]); break; + case OPC2_32_RRR_MADD_F: + gen_helper_fmadd(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], + cpu_gpr_d[r2], cpu_gpr_d[r3]); + break; + case OPC2_32_RRR_MSUB_F: + gen_helper_fmsub(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], + cpu_gpr_d[r2], cpu_gpr_d[r3]); + break; default: generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); } -- 2.7.4 (Apple Git-66)