From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50319) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b7cY3-000732-DB for qemu-devel@nongnu.org; Tue, 31 May 2016 01:49:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1b7cY0-0000cx-7F for qemu-devel@nongnu.org; Tue, 31 May 2016 01:49:03 -0400 Received: from mail.uni-paderborn.de ([131.234.142.9]:48577) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b7cXz-0000bp-TB for qemu-devel@nongnu.org; Tue, 31 May 2016 01:49:00 -0400 Received: from magmaria.uni-paderborn.de ([131.234.189.24] helo=localhost.localdomain) by mail.uni-paderborn.de with esmtp (Exim 4.84_2 amazonia) id 1b7cXv-00012N-9O for qemu-devel@nongnu.org; Tue, 31 May 2016 07:48:56 +0200 Received: from mail.uni-paderborn.de by magmaria with queue id 1139030-3 for qemu-devel@nongnu.org; Tue, 31 May 2016 05:48:55 GMT From: peer.adelt@c-lab.de Date: Tue, 31 May 2016 07:48:41 +0200 Message-Id: <1464673721-14578-1-git-send-email-peer.adelt@c-lab.de> Subject: [Qemu-devel] [PATCH v2 3/4] target-tricore: Added new MOV instruction variant List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: kbastian@mail.uni-paderborn.de, Peer Adelt From: Peer Adelt Puts the content of data register D[a] into E[c][63:32] and the content of data register D[b] into E[c][31:0]. Signed-off-by: Peer Adelt --- target-tricore/translate.c | 8 ++++++++ target-tricore/tricore-opcodes.h | 1 + 2 files changed, 9 insertions(+) diff --git a/target-tricore/translate.c b/target-tricore/translate.c index e66b433..960ee33 100644 --- a/target-tricore/translate.c +++ b/target-tricore/translate.c @@ -6224,6 +6224,14 @@ static void decode_rr_accumulator(CPUTriCoreState *env, DisasContext *ctx) case OPC2_32_RR_MOV: tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]); break; + case OPC2_32_RR_MOV_EXT: + if (tricore_feature(env, TRICORE_FEATURE_16)) { + tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); + tcg_gen_mov_tl(cpu_gpr_d[(r3+1)], cpu_gpr_d[r2]); + } else { + generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); + } + break; case OPC2_32_RR_NE: tcg_gen_setcond_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); diff --git a/target-tricore/tricore-opcodes.h b/target-tricore/tricore-opcodes.h index df666b0..2f25613 100644 --- a/target-tricore/tricore-opcodes.h +++ b/target-tricore/tricore-opcodes.h @@ -1062,6 +1062,7 @@ enum { OPC2_32_RR_MIN_H = 0x78, OPC2_32_RR_MIN_HU = 0x79, OPC2_32_RR_MOV = 0x1f, + OPC2_32_RR_MOV_EXT = 0x81, OPC2_32_RR_NE = 0x11, OPC2_32_RR_OR_EQ = 0x27, OPC2_32_RR_OR_GE = 0x2b, -- 2.7.4