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From: Michael Rolnik <mrolnik@gmail.com>
To: qemu-devel@nongnu.org
Cc: Michael Rolnik <rolnik@amazon.com>, Michael Rolnik <mrolnik@gmail.com>
Subject: [Qemu-devel] [PATCH 04/10] target-avr: adding instructions encodings
Date: Thu,  2 Jun 2016 23:06:56 +0300	[thread overview]
Message-ID: <1464898022-97990-4-git-send-email-rolnik@amazon.com> (raw)
In-Reply-To: <1464898022-97990-1-git-send-email-rolnik@amazon.com>

Signed-off-by: Michael Rolnik <mrolnik@gmail.com>
---
 target-avr/translate-inst.h | 838 ++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 838 insertions(+)
 create mode 100644 target-avr/translate-inst.h

diff --git a/target-avr/translate-inst.h b/target-avr/translate-inst.h
new file mode 100644
index 0000000..6bd180d
--- /dev/null
+++ b/target-avr/translate-inst.h
@@ -0,0 +1,838 @@
+
+#ifndef AVR_TRANSLATE_INST_H_
+#define AVR_TRANSLATE_INST_H_
+
+typedef struct DisasContext    DisasContext;
+
+int     avr_translate_NOP(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+
+int     avr_translate_MOVW(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+static inline uint32_t MOVW_Rr(uint32_t opcode)
+{
+    return extract32(opcode, 0, 4);
+}
+static inline uint32_t MOVW_Rd(uint32_t opcode)
+{
+    return extract32(opcode, 4, 4);
+}
+
+int     avr_translate_MULS(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+static inline uint32_t MULS_Rr(uint32_t opcode)
+{
+    return extract32(opcode, 0, 4);
+}
+static inline uint32_t MULS_Rd(uint32_t opcode)
+{
+    return extract32(opcode, 4, 4);
+}
+
+int     avr_translate_MULSU(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+static inline uint32_t MULSU_Rr(uint32_t opcode)
+{
+    return extract32(opcode, 0, 3);
+}
+static inline uint32_t MULSU_Rd(uint32_t opcode)
+{
+    return extract32(opcode, 4, 3);
+}
+
+int     avr_translate_FMUL(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+static inline uint32_t FMUL_Rr(uint32_t opcode)
+{
+    return extract32(opcode, 0, 3);
+}
+static inline uint32_t FMUL_Rd(uint32_t opcode)
+{
+    return extract32(opcode, 4, 3);
+}
+
+int     avr_translate_FMULS(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+static inline uint32_t FMULS_Rr(uint32_t opcode)
+{
+    return extract32(opcode, 0, 3);
+}
+static inline uint32_t FMULS_Rd(uint32_t opcode)
+{
+    return extract32(opcode, 4, 3);
+}
+
+int     avr_translate_FMULSU(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+static inline uint32_t FMULSU_Rr(uint32_t opcode)
+{
+    return extract32(opcode, 0, 3);
+}
+static inline uint32_t FMULSU_Rd(uint32_t opcode)
+{
+    return extract32(opcode, 4, 3);
+}
+
+int     avr_translate_CPC(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+static inline uint32_t CPC_lRr(uint32_t opcode)
+{
+    return extract32(opcode, 0, 4);
+}
+static inline uint32_t CPC_Rd(uint32_t opcode)
+{
+    return extract32(opcode, 4, 5);
+}
+static inline uint32_t CPC_hRr(uint32_t opcode)
+{
+    return extract32(opcode, 9, 1);
+}
+
+int     avr_translate_SBC(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+static inline uint32_t SBC_lRr(uint32_t opcode)
+{
+    return extract32(opcode, 0, 4);
+}
+static inline uint32_t SBC_Rd(uint32_t opcode)
+{
+    return extract32(opcode, 4, 5);
+}
+static inline uint32_t SBC_hRr(uint32_t opcode)
+{
+    return extract32(opcode, 9, 1);
+}
+
+int     avr_translate_ADD(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+static inline uint32_t ADD_lRr(uint32_t opcode)
+{
+    return extract32(opcode, 0, 4);
+}
+static inline uint32_t ADD_Rd(uint32_t opcode)
+{
+    return extract32(opcode, 4, 5);
+}
+static inline uint32_t ADD_hRr(uint32_t opcode)
+{
+    return extract32(opcode, 9, 1);
+}
+
+int     avr_translate_AND(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+static inline uint32_t AND_lRr(uint32_t opcode)
+{
+    return extract32(opcode, 0, 4);
+}
+static inline uint32_t AND_Rd(uint32_t opcode)
+{
+    return extract32(opcode, 4, 5);
+}
+static inline uint32_t AND_hRr(uint32_t opcode)
+{
+    return extract32(opcode, 9, 1);
+}
+
+int     avr_translate_EOR(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+static inline uint32_t EOR_lRr(uint32_t opcode)
+{
+    return extract32(opcode, 0, 4);
+}
+static inline uint32_t EOR_Rd(uint32_t opcode)
+{
+    return extract32(opcode, 4, 5);
+}
+static inline uint32_t EOR_hRr(uint32_t opcode)
+{
+    return extract32(opcode, 9, 1);
+}
+
+int     avr_translate_OR(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+static inline uint32_t OR_lRr(uint32_t opcode)
+{
+    return extract32(opcode, 0, 4);
+}
+static inline uint32_t OR_Rd(uint32_t opcode)
+{
+    return extract32(opcode, 4, 5);
+}
+static inline uint32_t OR_hRr(uint32_t opcode)
+{
+    return extract32(opcode, 9, 1);
+}
+
+int     avr_translate_MOV(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+static inline uint32_t MOV_lRr(uint32_t opcode)
+{
+    return extract32(opcode, 0, 4);
+}
+static inline uint32_t MOV_Rd(uint32_t opcode)
+{
+    return extract32(opcode, 4, 5);
+}
+static inline uint32_t MOV_hRr(uint32_t opcode)
+{
+    return extract32(opcode, 9, 1);
+}
+
+int     avr_translate_CPSE(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+static inline uint32_t CPSE_lRr(uint32_t opcode)
+{
+    return extract32(opcode, 0, 4);
+}
+static inline uint32_t CPSE_Rd(uint32_t opcode)
+{
+    return extract32(opcode, 4, 5);
+}
+static inline uint32_t CPSE_hRr(uint32_t opcode)
+{
+    return extract32(opcode, 9, 1);
+}
+
+int     avr_translate_CP(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+static inline uint32_t CP_lRr(uint32_t opcode)
+{
+    return extract32(opcode, 0, 4);
+}
+static inline uint32_t CP_Rd(uint32_t opcode)
+{
+    return extract32(opcode, 4, 5);
+}
+static inline uint32_t CP_hRr(uint32_t opcode)
+{
+    return extract32(opcode, 9, 1);
+}
+
+int     avr_translate_SUB(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+static inline uint32_t SUB_lRr(uint32_t opcode)
+{
+    return extract32(opcode, 0, 4);
+}
+static inline uint32_t SUB_Rd(uint32_t opcode)
+{
+    return extract32(opcode, 4, 5);
+}
+static inline uint32_t SUB_hRr(uint32_t opcode)
+{
+    return extract32(opcode, 9, 1);
+}
+
+int     avr_translate_ADC(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+static inline uint32_t ADC_lRr(uint32_t opcode)
+{
+    return extract32(opcode, 0, 4);
+}
+static inline uint32_t ADC_Rd(uint32_t opcode)
+{
+    return extract32(opcode, 4, 5);
+}
+static inline uint32_t ADC_hRr(uint32_t opcode)
+{
+    return extract32(opcode, 9, 1);
+}
+
+int     avr_translate_CPI(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+static inline uint32_t CPI_lImm(uint32_t opcode)
+{
+    return extract32(opcode, 0, 4);
+}
+static inline uint32_t CPI_Rd(uint32_t opcode)
+{
+    return extract32(opcode, 4, 4);
+}
+static inline uint32_t CPI_hImm(uint32_t opcode)
+{
+    return extract32(opcode, 8, 4);
+}
+
+int     avr_translate_SBCI(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+static inline uint32_t SBCI_lImm(uint32_t opcode)
+{
+    return extract32(opcode, 0, 4);
+}
+static inline uint32_t SBCI_Rd(uint32_t opcode)
+{
+    return extract32(opcode, 4, 4);
+}
+static inline uint32_t SBCI_hImm(uint32_t opcode)
+{
+    return extract32(opcode, 8, 4);
+}
+
+int     avr_translate_ORI(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+static inline uint32_t ORI_lImm(uint32_t opcode)
+{
+    return extract32(opcode, 0, 4);
+}
+static inline uint32_t ORI_Rd(uint32_t opcode)
+{
+    return extract32(opcode, 4, 4);
+}
+static inline uint32_t ORI_hImm(uint32_t opcode)
+{
+    return extract32(opcode, 8, 4);
+}
+
+int     avr_translate_SUBI(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+static inline uint32_t SUBI_lImm(uint32_t opcode)
+{
+    return extract32(opcode, 0, 4);
+}
+static inline uint32_t SUBI_Rd(uint32_t opcode)
+{
+    return extract32(opcode, 4, 4);
+}
+static inline uint32_t SUBI_hImm(uint32_t opcode)
+{
+    return extract32(opcode, 8, 4);
+}
+
+int     avr_translate_ANDI(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+static inline uint32_t ANDI_lImm(uint32_t opcode)
+{
+    return extract32(opcode, 0, 4);
+}
+static inline uint32_t ANDI_Rd(uint32_t opcode)
+{
+    return extract32(opcode, 4, 4);
+}
+static inline uint32_t ANDI_hImm(uint32_t opcode)
+{
+    return extract32(opcode, 8, 4);
+}
+
+int     avr_translate_LDDZ(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+static inline uint32_t LDDZ_lImm(uint32_t opcode)
+{
+    return extract32(opcode, 0, 3);
+}
+static inline uint32_t LDDZ_Rd(uint32_t opcode)
+{
+    return extract32(opcode, 4, 5);
+}
+static inline uint32_t LDDZ_mImm(uint32_t opcode)
+{
+    return extract32(opcode, 10, 2);
+}
+static inline uint32_t LDDZ_hImm(uint32_t opcode)
+{
+    return extract32(opcode, 13, 1);
+}
+
+int     avr_translate_LDDY(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+static inline uint32_t LDDY_lImm(uint32_t opcode)
+{
+    return extract32(opcode, 0, 3);
+}
+static inline uint32_t LDDY_Rd(uint32_t opcode)
+{
+    return extract32(opcode, 4, 5);
+}
+static inline uint32_t LDDY_mImm(uint32_t opcode)
+{
+    return extract32(opcode, 10, 2);
+}
+static inline uint32_t LDDY_hImm(uint32_t opcode)
+{
+    return extract32(opcode, 13, 1);
+}
+
+int     avr_translate_STDZ(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+static inline uint32_t STDZ_lImm(uint32_t opcode)
+{
+    return extract32(opcode, 0, 3);
+}
+static inline uint32_t STDZ_Rd(uint32_t opcode)
+{
+    return extract32(opcode, 4, 5);
+}
+static inline uint32_t STDZ_mImm(uint32_t opcode)
+{
+    return extract32(opcode, 10, 2);
+}
+static inline uint32_t STDZ_hImm(uint32_t opcode)
+{
+    return extract32(opcode, 13, 1);
+}
+
+int     avr_translate_STDY(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+static inline uint32_t STDY_lImm(uint32_t opcode)
+{
+    return extract32(opcode, 0, 3);
+}
+static inline uint32_t STDY_Rd(uint32_t opcode)
+{
+    return extract32(opcode, 4, 5);
+}
+static inline uint32_t STDY_mImm(uint32_t opcode)
+{
+    return extract32(opcode, 10, 2);
+}
+static inline uint32_t STDY_hImm(uint32_t opcode)
+{
+    return extract32(opcode, 13, 1);
+}
+
+int     avr_translate_LDS(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+static inline uint32_t LDS_Imm(uint32_t opcode)
+{
+    return extract32(opcode, 0, 16);
+}
+static inline uint32_t LDS_Rd(uint32_t opcode)
+{
+    return extract32(opcode, 20, 5);
+}
+
+int     avr_translate_LDZ2(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+static inline uint32_t LDZ2_Rd(uint32_t opcode)
+{
+    return extract32(opcode, 4, 5);
+}
+
+int     avr_translate_LDZ3(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+static inline uint32_t LDZ3_Rd(uint32_t opcode)
+{
+    return extract32(opcode, 4, 5);
+}
+
+int     avr_translate_LPM2(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+static inline uint32_t LPM2_Rd(uint32_t opcode)
+{
+    return extract32(opcode, 4, 5);
+}
+
+int     avr_translate_LPMX(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+static inline uint32_t LPMX_Rd(uint32_t opcode)
+{
+    return extract32(opcode, 4, 5);
+}
+
+int     avr_translate_ELPM2(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+static inline uint32_t ELPM2_Rd(uint32_t opcode)
+{
+    return extract32(opcode, 4, 5);
+}
+
+int     avr_translate_ELPMX(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+static inline uint32_t ELPMX_Rd(uint32_t opcode)
+{
+    return extract32(opcode, 4, 5);
+}
+
+int     avr_translate_LDY2(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+static inline uint32_t LDY2_Rd(uint32_t opcode)
+{
+    return extract32(opcode, 4, 5);
+}
+
+int     avr_translate_LDY3(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+static inline uint32_t LDY3_Rd(uint32_t opcode)
+{
+    return extract32(opcode, 4, 5);
+}
+
+int     avr_translate_LDX1(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+static inline uint32_t LDX1_Rd(uint32_t opcode)
+{
+    return extract32(opcode, 4, 5);
+}
+
+int     avr_translate_LDX2(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+static inline uint32_t LDX2_Rd(uint32_t opcode)
+{
+    return extract32(opcode, 4, 5);
+}
+
+int     avr_translate_LDX3(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+static inline uint32_t LDX3_Rd(uint32_t opcode)
+{
+    return extract32(opcode, 4, 5);
+}
+
+int     avr_translate_POP(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+static inline uint32_t POP_Rd(uint32_t opcode)
+{
+    return extract32(opcode, 4, 5);
+}
+
+int     avr_translate_STS(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+static inline uint32_t STS_Imm(uint32_t opcode)
+{
+    return extract32(opcode, 0, 16);
+}
+static inline uint32_t STS_Rd(uint32_t opcode)
+{
+    return extract32(opcode, 20, 5);
+}
+
+int     avr_translate_STZ2(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+static inline uint32_t STZ2_Rd(uint32_t opcode)
+{
+    return extract32(opcode, 4, 5);
+}
+
+int     avr_translate_STZ3(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+static inline uint32_t STZ3_Rd(uint32_t opcode)
+{
+    return extract32(opcode, 4, 5);
+}
+
+int     avr_translate_XCH(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+static inline uint32_t XCH_Rd(uint32_t opcode)
+{
+    return extract32(opcode, 4, 5);
+}
+
+int     avr_translate_LAS(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+static inline uint32_t LAS_Rr(uint32_t opcode)
+{
+    return extract32(opcode, 4, 5);
+}
+
+int     avr_translate_LAC(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+static inline uint32_t LAC_Rr(uint32_t opcode)
+{
+    return extract32(opcode, 4, 5);
+}
+
+int     avr_translate_LAT(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+static inline uint32_t LAT_Rr(uint32_t opcode)
+{
+    return extract32(opcode, 4, 5);
+}
+
+int     avr_translate_STY2(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+static inline uint32_t STY2_Rd(uint32_t opcode)
+{
+    return extract32(opcode, 4, 5);
+}
+
+int     avr_translate_STY3(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+static inline uint32_t STY3_Rd(uint32_t opcode)
+{
+    return extract32(opcode, 4, 5);
+}
+
+int     avr_translate_STX1(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+static inline uint32_t STX1_Rr(uint32_t opcode)
+{
+    return extract32(opcode, 4, 5);
+}
+
+int     avr_translate_STX2(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+static inline uint32_t STX2_Rr(uint32_t opcode)
+{
+    return extract32(opcode, 4, 5);
+}
+
+int     avr_translate_STX3(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+static inline uint32_t STX3_Rr(uint32_t opcode)
+{
+    return extract32(opcode, 4, 5);
+}
+
+int     avr_translate_PUSH(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+static inline uint32_t PUSH_Rd(uint32_t opcode)
+{
+    return extract32(opcode, 4, 5);
+}
+
+int     avr_translate_COM(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+static inline uint32_t COM_Rd(uint32_t opcode)
+{
+    return extract32(opcode, 4, 5);
+}
+
+int     avr_translate_NEG(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+static inline uint32_t NEG_Rd(uint32_t opcode)
+{
+    return extract32(opcode, 4, 5);
+}
+
+int     avr_translate_SWAP(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+static inline uint32_t SWAP_Rd(uint32_t opcode)
+{
+    return extract32(opcode, 4, 5);
+}
+
+int     avr_translate_INC(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+static inline uint32_t INC_Rd(uint32_t opcode)
+{
+    return extract32(opcode, 4, 5);
+}
+
+int     avr_translate_ASR(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+static inline uint32_t ASR_Rd(uint32_t opcode)
+{
+    return extract32(opcode, 4, 5);
+}
+
+int     avr_translate_LSR(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+static inline uint32_t LSR_Rd(uint32_t opcode)
+{
+    return extract32(opcode, 4, 5);
+}
+
+int     avr_translate_ROR(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+static inline uint32_t ROR_Rd(uint32_t opcode)
+{
+    return extract32(opcode, 4, 5);
+}
+
+int     avr_translate_BSET(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+static inline uint32_t BSET_Bit(uint32_t opcode)
+{
+    return extract32(opcode, 4, 3);
+}
+
+int     avr_translate_IJMP(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+
+int     avr_translate_EIJMP(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+
+int     avr_translate_BCLR(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+static inline uint32_t BCLR_Bit(uint32_t opcode)
+{
+    return extract32(opcode, 4, 3);
+}
+
+int     avr_translate_RET(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+
+int     avr_translate_RETI(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+
+int     avr_translate_ICALL(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+
+int     avr_translate_EICALL(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+
+int     avr_translate_SLEEP(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+
+int     avr_translate_BREAK(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+
+int     avr_translate_WDR(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+
+int     avr_translate_LPM1(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+
+int     avr_translate_ELPM1(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+
+int     avr_translate_SPM(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+
+int     avr_translate_SPMX(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+
+int     avr_translate_DEC(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+static inline uint32_t DEC_Rd(uint32_t opcode)
+{
+    return extract32(opcode, 4, 5);
+}
+
+int     avr_translate_DES(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+static inline uint32_t DES_Imm(uint32_t opcode)
+{
+    return extract32(opcode, 4, 4);
+}
+
+int     avr_translate_JMP(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+static inline uint32_t JMP_lImm(uint32_t opcode)
+{
+    return extract32(opcode, 0, 17);
+}
+static inline uint32_t JMP_hImm(uint32_t opcode)
+{
+    return extract32(opcode, 20, 5);
+}
+
+int     avr_translate_CALL(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+static inline uint32_t CALL_lImm(uint32_t opcode)
+{
+    return extract32(opcode, 0, 17);
+}
+static inline uint32_t CALL_hImm(uint32_t opcode)
+{
+    return extract32(opcode, 20, 5);
+}
+
+int     avr_translate_ADIW(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+static inline uint32_t ADIW_lImm(uint32_t opcode)
+{
+    return extract32(opcode, 0, 4);
+}
+static inline uint32_t ADIW_Rd(uint32_t opcode)
+{
+    return extract32(opcode, 4, 2);
+}
+static inline uint32_t ADIW_hImm(uint32_t opcode)
+{
+    return extract32(opcode, 6, 2);
+}
+
+int     avr_translate_SBIW(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+static inline uint32_t SBIW_lImm(uint32_t opcode)
+{
+    return extract32(opcode, 0, 4);
+}
+static inline uint32_t SBIW_Rd(uint32_t opcode)
+{
+    return extract32(opcode, 4, 2);
+}
+static inline uint32_t SBIW_hImm(uint32_t opcode)
+{
+    return extract32(opcode, 6, 2);
+}
+
+int     avr_translate_CBI(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+static inline uint32_t CBI_Bit(uint32_t opcode)
+{
+    return extract32(opcode, 0, 3);
+}
+static inline uint32_t CBI_Imm(uint32_t opcode)
+{
+    return extract32(opcode, 3, 5);
+}
+
+int     avr_translate_SBIC(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+static inline uint32_t SBIC_Bit(uint32_t opcode)
+{
+    return extract32(opcode, 0, 3);
+}
+static inline uint32_t SBIC_Imm(uint32_t opcode)
+{
+    return extract32(opcode, 3, 5);
+}
+
+int     avr_translate_SBI(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+static inline uint32_t SBI_Bit(uint32_t opcode)
+{
+    return extract32(opcode, 0, 3);
+}
+static inline uint32_t SBI_Imm(uint32_t opcode)
+{
+    return extract32(opcode, 3, 5);
+}
+
+int     avr_translate_SBIS(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+static inline uint32_t SBIS_Bit(uint32_t opcode)
+{
+    return extract32(opcode, 0, 3);
+}
+static inline uint32_t SBIS_Imm(uint32_t opcode)
+{
+    return extract32(opcode, 3, 5);
+}
+
+int     avr_translate_MUL(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+static inline uint32_t MUL_lRr(uint32_t opcode)
+{
+    return extract32(opcode, 0, 4);
+}
+static inline uint32_t MUL_Rd(uint32_t opcode)
+{
+    return extract32(opcode, 4, 5);
+}
+static inline uint32_t MUL_hRr(uint32_t opcode)
+{
+    return extract32(opcode, 9, 1);
+}
+
+int     avr_translate_IN(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+static inline uint32_t IN_lImm(uint32_t opcode)
+{
+    return extract32(opcode, 0, 4);
+}
+static inline uint32_t IN_Rd(uint32_t opcode)
+{
+    return extract32(opcode, 4, 5);
+}
+static inline uint32_t IN_hImm(uint32_t opcode)
+{
+    return extract32(opcode, 9, 2);
+}
+
+int     avr_translate_OUT(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+static inline uint32_t OUT_lImm(uint32_t opcode)
+{
+    return extract32(opcode, 0, 4);
+}
+static inline uint32_t OUT_Rd(uint32_t opcode)
+{
+    return extract32(opcode, 4, 5);
+}
+static inline uint32_t OUT_hImm(uint32_t opcode)
+{
+    return extract32(opcode, 9, 2);
+}
+
+int     avr_translate_RJMP(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+static inline uint32_t RJMP_Imm(uint32_t opcode)
+{
+    return extract32(opcode, 0, 12);
+}
+
+int     avr_translate_LDI(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+static inline uint32_t LDI_lImm(uint32_t opcode)
+{
+    return extract32(opcode, 0, 4);
+}
+static inline uint32_t LDI_Rd(uint32_t opcode)
+{
+    return extract32(opcode, 4, 4);
+}
+static inline uint32_t LDI_hImm(uint32_t opcode)
+{
+    return extract32(opcode, 8, 4);
+}
+
+int     avr_translate_RCALL(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+static inline uint32_t RCALL_Imm(uint32_t opcode)
+{
+    return extract32(opcode, 0, 12);
+}
+
+int     avr_translate_BRBS(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+static inline uint32_t BRBS_Bit(uint32_t opcode)
+{
+    return extract32(opcode, 0, 3);
+}
+static inline uint32_t BRBS_Imm(uint32_t opcode)
+{
+    return extract32(opcode, 3, 7);
+}
+
+int     avr_translate_BRBC(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+static inline uint32_t BRBC_Bit(uint32_t opcode)
+{
+    return extract32(opcode, 0, 3);
+}
+static inline uint32_t BRBC_Imm(uint32_t opcode)
+{
+    return extract32(opcode, 3, 7);
+}
+
+int     avr_translate_BLD(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+static inline uint32_t BLD_Bit(uint32_t opcode)
+{
+    return extract32(opcode, 0, 3);
+}
+static inline uint32_t BLD_Rd(uint32_t opcode)
+{
+    return extract32(opcode, 4, 5);
+}
+
+int     avr_translate_BST(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+static inline uint32_t BST_Bit(uint32_t opcode)
+{
+    return extract32(opcode, 0, 3);
+}
+static inline uint32_t BST_Rd(uint32_t opcode)
+{
+    return extract32(opcode, 4, 5);
+}
+
+int     avr_translate_SBRC(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+static inline uint32_t SBRC_Bit(uint32_t opcode)
+{
+    return extract32(opcode, 0, 3);
+}
+static inline uint32_t SBRC_Rr(uint32_t opcode)
+{
+    return extract32(opcode, 4, 5);
+}
+
+int     avr_translate_SBRS(CPUAVRState *env, DisasContext* ctx, uint32_t opcode);
+static inline uint32_t SBRS_Bit(uint32_t opcode)
+{
+    return extract32(opcode, 0, 3);
+}
+static inline uint32_t SBRS_Rr(uint32_t opcode)
+{
+    return extract32(opcode, 4, 5);
+}
+
+
+#endif
-- 
2.4.9 (Apple Git-60)

  parent reply	other threads:[~2016-06-02 20:07 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-06-02 20:06 [Qemu-devel] [PATCH 01/10] target-avr: AVR cores support is added. 1. basic CPU structure 2. registers 3. no instructions Michael Rolnik
2016-06-02 20:06 ` [Qemu-devel] [PATCH 02/10] target-avr: adding AVR CPU features/flavors Michael Rolnik
2016-06-04 20:02   ` Richard Henderson
2016-06-02 20:06 ` [Qemu-devel] [PATCH 03/10] target-avr: adding a sample AVR board Michael Rolnik
2016-06-02 20:06 ` Michael Rolnik [this message]
2016-06-04 22:17   ` [Qemu-devel] [PATCH 04/10] target-avr: adding instructions encodings Richard Henderson
2016-06-05  5:09     ` Michael Rolnik
2016-06-05 16:08       ` Richard Henderson
2016-06-02 20:06 ` [Qemu-devel] [PATCH 05/10] target-avr: adding AVR interrupt handling Michael Rolnik
2016-06-04 22:26   ` Richard Henderson
2016-06-05  5:10     ` Michael Rolnik
2016-06-02 20:06 ` [Qemu-devel] [PATCH 06/10] target-avr: adding helpers for IN, OUT, SLEEP, WBR & unsupported instructions Michael Rolnik
2016-06-04 22:48   ` Richard Henderson
2016-06-05  5:10     ` Michael Rolnik
2016-06-02 20:06 ` [Qemu-devel] [PATCH 07/10] target-avr: adding instruction decoder Michael Rolnik
2016-06-04 23:00   ` Richard Henderson
2016-06-05  5:18     ` Michael Rolnik
2016-06-02 20:07 ` [Qemu-devel] [PATCH 08/10] target-avr: adding instruction translation Michael Rolnik
2016-06-05  3:27   ` Richard Henderson
2016-06-05 21:47     ` Michael Rolnik
2016-06-05 23:34       ` Richard Henderson
2016-06-06  6:52         ` Michael Rolnik
2016-06-06 19:17           ` Richard Henderson
2016-06-06 19:34             ` Michael Rolnik
2016-06-02 20:07 ` [Qemu-devel] [PATCH 09/10] target-avr: updating translate.c to use instructions translation Michael Rolnik
2016-06-05  3:33   ` Richard Henderson
2016-06-05 21:49     ` Michael Rolnik
2016-06-02 20:07 ` [Qemu-devel] [PATCH 10/10] target-avr: fixing code style Michael Rolnik
2016-06-02 23:10   ` Peter Maydell
2016-06-04 17:41     ` Richard Henderson
2016-06-04 18:34       ` Michael Rolnik
2016-06-04 22:33         ` Richard Henderson
2016-06-05 12:27           ` Peter Maydell
2016-06-05  3:34   ` Richard Henderson
2016-06-04 19:55 ` [Qemu-devel] [PATCH 01/10] target-avr: AVR cores support is added. 1. basic CPU structure 2. registers 3. no instructions Richard Henderson
  -- strict thread matches above, loose matches on Subject: below --
2016-06-02 20:03 Michael Rolnik
2016-06-02 20:04 ` [Qemu-devel] [PATCH 04/10] target-avr: adding instructions encodings Michael Rolnik

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