From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46732) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b8dAm-0006rb-8r for qemu-devel@nongnu.org; Thu, 02 Jun 2016 20:41:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1b8dAj-0007Yo-41 for qemu-devel@nongnu.org; Thu, 02 Jun 2016 20:41:12 -0400 Received: from mail-wm0-x241.google.com ([2a00:1450:400c:c09::241]:36589) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b8dAi-0007YP-Sv for qemu-devel@nongnu.org; Thu, 02 Jun 2016 20:41:09 -0400 Received: by mail-wm0-x241.google.com with SMTP id a20so8286779wma.3 for ; Thu, 02 Jun 2016 17:41:08 -0700 (PDT) Received: from a0999b0126e1.ant.amazon.com ([94.230.86.227]) by smtp.gmail.com with ESMTPSA id i190sm42677210wmf.10.2016.06.02.17.41.06 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 02 Jun 2016 17:41:07 -0700 (PDT) From: Michael Rolnik Date: Fri, 3 Jun 2016 03:40:11 +0300 Message-Id: <1464914420-17875-1-git-send-email-rolnik@amazon.com> Subject: [Qemu-devel] AVR cores List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org This series of patches adds 8bit AVR cores to QEMU. All instruction, except BREAK/DES/SPM/SPMX, are implemented. Not fully tested yet. However I was able to execute simple code with functions. e.g fibonacci calculation. This series of patches include a non real, sample board. No fuses support yet. PC is set to 0 at reset. the patches include the following 1. just a basic 8bit AVR CPU, without instruction decoding or translation 2. CPU features which allow define the following 8bit AVR cores avr1 avr2 avr25 avr3 avr31 avr35 avr4 avr5 avr51 avr6 xmega2 xmega4 xmega5 xmega6 xmega7 3. a difinition of sample machine with SRAM, FLASH and CPU which allows to execute simple code 4. encoding for all AVR instructions 5. interrupt handling 6. helpers for IN, OUT, SLEEP, WBR & unsupported instructions 7. a decoder which given an opcode decides what istruction it is 8. translation of AVR instruction into TCG 9. all features together