From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46823) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b8dAs-0006vB-AN for qemu-devel@nongnu.org; Thu, 02 Jun 2016 20:41:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1b8dAq-0007bi-7s for qemu-devel@nongnu.org; Thu, 02 Jun 2016 20:41:17 -0400 Received: from mail-wm0-x241.google.com ([2a00:1450:400c:c09::241]:33084) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b8dAp-0007bQ-TO for qemu-devel@nongnu.org; Thu, 02 Jun 2016 20:41:16 -0400 Received: by mail-wm0-x241.google.com with SMTP id a136so19896946wme.0 for ; Thu, 02 Jun 2016 17:41:15 -0700 (PDT) From: Michael Rolnik Date: Fri, 3 Jun 2016 03:40:16 +0300 Message-Id: <1464914420-17875-6-git-send-email-rolnik@amazon.com> In-Reply-To: <1464914420-17875-1-git-send-email-rolnik@amazon.com> References: <1464914420-17875-1-git-send-email-rolnik@amazon.com> Subject: [Qemu-devel] [PATCH 5/9] target-avr: adding AVR interrupt handling List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Michael Rolnik , Michael Rolnik Signed-off-by: Michael Rolnik --- target-avr/helper.c | 64 ++++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 63 insertions(+), 1 deletion(-) diff --git a/target-avr/helper.c b/target-avr/helper.c index fbab91d..bb47a87 100644 --- a/target-avr/helper.c +++ b/target-avr/helper.c @@ -31,11 +31,73 @@ bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { - return false; + CPUClass *cc = CPU_GET_CLASS(cs); + AVRCPU *cpu = AVR_CPU(cs); + CPUAVRState *env = &cpu->env; + + bool ret = false; + + if (interrupt_request & CPU_INTERRUPT_RESET) { + if (cpu_interrupts_enabled(env)) { + cs->exception_index = EXCP_RESET; + cc->do_interrupt(cs); + + cs->interrupt_request &= ~CPU_INTERRUPT_RESET; + + ret = true; + } + } + if (interrupt_request & CPU_INTERRUPT_HARD) { + if (cpu_interrupts_enabled(env) && env->intsrc != 0) { + int index = __builtin_ffs(env->intsrc) - 1; + cs->exception_index = EXCP_INT(index); + cc->do_interrupt(cs); + + env->intsrc &= env->intsrc - 1; /* clear the interrupt */ + cs->interrupt_request &= ~CPU_INTERRUPT_HARD; + + ret = true; + } + } + return ret; } void avr_cpu_do_interrupt(CPUState *cs) { + AVRCPU *cpu = AVR_CPU(cs); + CPUAVRState *env = &cpu->env; + + uint32_t ret = env->pc; + int vector; + int size = avr_feature(env, AVR_FEATURE_JMP_CALL) ? 2 : 1; + int base = 0; /* TODO: where to get it */ + + if (cs->exception_index == EXCP_RESET) { + vector = 0; + } else if (env->intsrc != 0) { + vector = __builtin_ffs(env->intsrc); + } + + if (avr_feature(env, AVR_FEATURE_3_BYTE_PC)) { + stb_phys(cs->as, env->sp--, (ret & 0x0000ff)); + stb_phys(cs->as, env->sp--, (ret & 0x00ff00) >> 8); + stb_phys(cs->as, env->sp--, (ret & 0xff0000) >> 16); + + env->pc = base + vector * size; + } else if (avr_feature(env, AVR_FEATURE_2_BYTE_PC)) { + stb_phys(cs->as, env->sp--, (ret & 0x0000ff)); + stb_phys(cs->as, env->sp--, (ret & 0x00ff00) >> 8); + + env->pc = base + vector * size; + } else { + stb_phys(cs->as, env->sp--, (ret & 0x0000ff)); + + env->pc = base + vector * size; + } + + env->sregI = 0; /* clear Global Interrupt Flag */ + + cs->exception_index = -1; } int avr_cpu_memory_rw_debug(CPUState *cs, vaddr addr, uint8_t *buf, int len, bool is_write) -- 2.4.9 (Apple Git-60)