From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49175) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b8nyB-0001xn-5G for qemu-devel@nongnu.org; Fri, 03 Jun 2016 08:13:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1b8ny3-0002p8-Hp for qemu-devel@nongnu.org; Fri, 03 Jun 2016 08:12:55 -0400 Received: from 9.mo1.mail-out.ovh.net ([178.32.108.172]:50708) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b8ny3-0002oQ-7K for qemu-devel@nongnu.org; Fri, 03 Jun 2016 08:12:47 -0400 Received: from player729.ha.ovh.net (b9.ovh.net [213.186.33.59]) by mo1.mail-out.ovh.net (Postfix) with ESMTP id 50AF410F0145 for ; Fri, 3 Jun 2016 14:12:46 +0200 (CEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Fri, 3 Jun 2016 14:11:19 +0200 Message-Id: <1464955880-10176-3-git-send-email-clg@kaod.org> In-Reply-To: <1464955880-10176-1-git-send-email-clg@kaod.org> References: <1464955880-10176-1-git-send-email-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH 2/3] ppc: Better figure out if processor has HV mode List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: David Gibson Cc: Benjamin Herrenschmidt , Mark Cave-Ayland , qemu-devel@nongnu.org, qemu-ppc@nongnu.org, Cedric Le Goater From: Benjamin Herrenschmidt We use an env. flag which is set to the initial value of MSR_HVB in the msr_mask. We also adjust the POWER8 mask to set SHV. Also use this to adjust ctx.hv so that it is *set* when the processor doesn't have an HV mode (970 with Apple mode for example), thus enabling hypervisor instructions/SPRs. Signed-off-by: Benjamin Herrenschmidt Reviewed-by: David Gibson [clg: ctx.hv used to be defined only for the hypervisor kernel (HV=3D1|PR=3D0). It is now defined also when PR=3D1 and conditions = are fixed accordingly. stripped unwanted tabs.] Signed-off-by: C=C3=A9dric Le Goater --- target-ppc/cpu.h | 4 ++++ target-ppc/translate.c | 4 +++- target-ppc/translate_init.c | 19 +++++++++++++++---- 3 files changed, 22 insertions(+), 5 deletions(-) diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 98a24a50f3b5..d8f8f7e233c7 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -1050,6 +1050,10 @@ struct CPUPPCState { hwaddr mpic_iack; /* true when the external proxy facility mode is enabled */ bool mpic_proxy; + /* set when the processor has an HV mode, thus HV priv + * instructions and SPRs are diallowed if MSR:HV is 0 + */ + bool has_hv_mode; #endif =20 /* Those resources are used only during code translation */ diff --git a/target-ppc/translate.c b/target-ppc/translate.c index fe10bf8774cb..ad262523abca 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -11478,8 +11478,10 @@ void gen_intermediate_code(CPUPPCState *env, str= uct TranslationBlock *tb) ctx.exception =3D POWERPC_EXCP_NONE; ctx.spr_cb =3D env->spr_cb; ctx.pr =3D msr_pr; - ctx.hv =3D !msr_pr && msr_hv; ctx.mem_idx =3D env->dmmu_idx; +#if !defined(CONFIG_USER_ONLY) + ctx.hv =3D msr_hv || !env->has_hv_mode; +#endif ctx.insns_flags =3D env->insns_flags; ctx.insns_flags2 =3D env->insns_flags2; ctx.access_type =3D -1; diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index 83010768ea05..55f855309806 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -8450,6 +8450,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | PPC2_TM; pcc->msr_mask =3D (1ull << MSR_SF) | + (1ull << MSR_SHV) | (1ull << MSR_TM) | (1ull << MSR_VR) | (1ull << MSR_VSX) | @@ -9854,10 +9855,7 @@ static void ppc_cpu_reset(CPUState *s) pcc->parent_reset(s); =20 msr =3D (target_ulong)0; - if (0) { - /* XXX: find a suitable condition to enable the hypervisor mode = */ - msr |=3D (target_ulong)MSR_HVB; - } + msr |=3D (target_ulong)MSR_HVB; msr |=3D (target_ulong)0 << MSR_AP; /* TO BE CHECKED */ msr |=3D (target_ulong)0 << MSR_SA; /* TO BE CHECKED */ msr |=3D (target_ulong)1 << MSR_EP; @@ -9958,6 +9956,19 @@ static void ppc_cpu_initfn(Object *obj) env->bfd_mach =3D pcc->bfd_mach; env->check_pow =3D pcc->check_pow; =20 + /* Mark HV mode as supported if the CPU has an MSR_HV bit + * in the msr_mask. The mask can later be cleared by PAPR + * mode but the hv mode support will remain, thus enforcing + * that we cannot use priv. instructions in guest in PAPR + * mode. For 970 we currently simply don't set HV in msr_mask + * thus simulating an "Apple mode" 970. If we ever want to + * support 970 HV mode, we'll have to add a processor attribute + * of some sort. + */ +#if !defined(CONFIG_USER_ONLY) + env->has_hv_mode =3D !!(env->msr_mask & MSR_HVB); +#endif + #if defined(TARGET_PPC64) if (pcc->sps) { env->sps =3D *pcc->sps; --=20 2.1.4