From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: Aleksandar Rakic <aleksandar.rakic@htecgroup.com>,
"qemu-devel@nongnu.org" <qemu-devel@nongnu.org>
Cc: Djordje Todorovic <Djordje.Todorovic@htecgroup.com>,
"cfu@mips.com" <cfu@mips.com>,
"arikalo@gmail.com" <arikalo@gmail.com>,
"peter.maydell@linaro.org" <peter.maydell@linaro.org>
Subject: Re: [PATCH v2 7/8] target/mips: Enable MSA ASE for mips32r6-generic
Date: Fri, 25 Oct 2024 16:18:53 -0300 [thread overview]
Message-ID: <1464da3f-e9ee-43e1-9b3e-c405b91e0144@linaro.org> (raw)
In-Reply-To: <AM9PR09MB485153B7CB706E188DED763484402@AM9PR09MB4851.eurprd09.prod.outlook.com>
On 18/10/24 10:20, Aleksandar Rakic wrote:
> Enable MSA ASE for mips32r6-generic CPU.
Commit 4b3bcd016d8 added this comment:
/* A generic CPU supporting MIPS32 Release 6 ISA.
FIXME: Support IEEE 754-2008 FP.
Eventually this should be replaced by a
real CPU model. */
.name = "mips32r6-generic",
I'd rather we model a real mips32r6 core. Or for generic models
enable a feature using a CLI flag, i.e.:
-cpu mips32r6-generic,+msa / -cpu mips32r6-generic,msa=on
But this would need quite some rework.
> Cherry-picked 0186e83a0613e90aff6d4c12c91cdb080d695d37
> from https://github.com/MIPS/gnutools-qemu
>
> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
> Signed-off-by: Faraz Shahbazker <fshahbazker@wavecomp.com>
> Signed-off-by: Aleksandar Rakic <aleksandar.rakic@htecgroup.com>
> ---
> target/mips/cpu-defs.c.inc | 8 +++++---
> 1 file changed, 5 insertions(+), 3 deletions(-)
Patch queued.
prev parent reply other threads:[~2024-10-25 19:19 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-18 13:20 [PATCH v2 7/8] target/mips: Enable MSA ASE for mips32r6-generic Aleksandar Rakic
2024-10-19 7:46 ` Aleksandar Rikalo
2024-10-25 19:18 ` Philippe Mathieu-Daudé [this message]
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