From mboxrd@z Thu Jan  1 00:00:00 1970
Received: from eggs.gnu.org ([2001:4830:134:3::10]:49949)
	by lists.gnu.org with esmtp (Exim 4.71)
	(envelope-from <benh@kernel.crashing.org>) id 1b9le4-0002kC-P2
	for qemu-devel@nongnu.org; Sun, 05 Jun 2016 23:56:09 -0400
Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)
	(envelope-from <benh@kernel.crashing.org>) id 1b9le3-0001jS-Sb
	for qemu-devel@nongnu.org; Sun, 05 Jun 2016 23:56:08 -0400
Message-ID: <1465185333.4274.25.camel@kernel.crashing.org>
From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Date: Mon, 06 Jun 2016 13:55:33 +1000
In-Reply-To: <20160606011726.GB9226@voom.fritz.box>
References: <1464955880-10176-1-git-send-email-clg@kaod.org>
	<20160606011726.GB9226@voom.fritz.box>
Content-Type: text/plain; charset="UTF-8"
Mime-Version: 1.0
Content-Transfer-Encoding: quoted-printable
Subject: Re: [Qemu-devel] [PATCH 0/3] ppc: complete the new HV mode
List-Id: <qemu-devel.nongnu.org>
List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>
List-Archive: <http://lists.nongnu.org/archive/html/qemu-devel/>
List-Post: <mailto:qemu-devel@nongnu.org>
List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help>
List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=subscribe>
To: David Gibson <david@gibson.dropbear.id.au>, =?ISO-8859-1?Q?C=E9dric?= Le Goater <clg@kaod.org>
Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>, qemu-devel@nongnu.org, qemu-ppc@nongnu.org

On Mon, 2016-06-06 at 11:17 +1000, David Gibson wrote:
> On Fri, Jun 03, 2016 at 02:11:17PM +0200, C=C3=A9dric Le Goater wrote:
> >=20
> > This is follow up to complete the serie "ppc: preparing pnv landing
> > (round 2)" plus a little fix on instruction privileges.
> >=20
> > Tested on a POWER8 pserie guest and on mac99.
> >=20
> > Benjamin Herrenschmidt (2):
> > =C2=A0 ppc: Fix hreg_store_msr() so that non-HV mode cannot alter MSR=
:HV
> > =C2=A0 ppc: Better figure out if processor has HV mode
> >=20
> > C=C3=A9dric Le Goater (1):
> > =C2=A0 ppc: fix hrfid, tlbia and slbia privilege
> I've applied this series to ppc-for-2.7, swapping the order of patches
> 1 & 2 as Marc requested.=C2=A0=C2=A0I've also applied the extra patch t=
o fix tlb
> flushing on 32-bit cpus.=C2=A0=C2=A0I aim to send a pull request once I=
've done
> my usual tests.
>=20
I'm not sure that 32-bit patch is correct. We shouldn't have to flush
on IR/DR transitions at all, that's the whole point of the split I/D
code.

I think something else is wrong.

Cheers,
Ben.