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Message-ID: <1465206764.4274.45.camel@kernel.crashing.org>
From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Date: Mon, 06 Jun 2016 19:52:44 +1000
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Subject: [Qemu-devel] [PATCH 1/2] ppc: Properly tag the translation cache
 based on MMU mode
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To: qemu-ppc@nongnu.org
Cc: qemu-devel@nongnu.org, David Gibson <david@gibson.dropbear.id.au>, =?ISO-8859-1?Q?C=E9dric?= Le Goater <clg@kaod.org>, Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>

We used to always flush the TLB when changing relocation mode in
MSR:IR and MSR:DR (ie. MMU on/off for Instructions and Data).

We don't anymore since we have split mmu_idx for instruction and data.

However, since we hard code the mmu_idx in the translated code, we
now need to also make sure MSR:IR and MSR:DR are part of the hflags
used to tag translated code, so that we use different translated
code for different MMU settings.

Darwin gets hurt by this problem.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
=C2=A0target-ppc/helper_regs.h | 2 +-
=C2=A01 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target-ppc/helper_regs.h b/target-ppc/helper_regs.h
index 12af61c..104b690 100644
--- a/target-ppc/helper_regs.h
+++ b/target-ppc/helper_regs.h
@@ -95,7 +95,7 @@ static inline void hreg_compute_hflags(CPUPPCState *env=
)
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0/* We 'forget' FE0 & FE1: we'll never gener=
ate imprecise exceptions */
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0hflags_mask =3D (1 << MSR_VR) | (1 << MSR_A=
P) | (1 << MSR_SA) |
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0(1 << MSR_PR) | (1 =
<< MSR_FP) | (1 << MSR_SE) | (1 << MSR_BE) |
-=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0(1 << MSR_LE) | (1 << MS=
R_VSX);
+=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0(1 << MSR_LE) | (1 << MS=
R_VSX) | (1 << MSR_IR) | (1 << MSR_DR);
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0hflags_mask |=3D (1ULL << MSR_CM) | (1ULL <=
< MSR_SF) | MSR_HVB;
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0hreg_compute_mem_idx(env);
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0env->hflags =3D env->msr & hflags_mask;