From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL v2 00/25] target-arm queue
Date: Mon, 6 Jun 2016 17:02:32 +0100 [thread overview]
Message-ID: <1465228952-7883-1-git-send-email-peter.maydell@linaro.org> (raw)
Whoops, v1 didn't build on clang (warning about unused functions)
or 32-bit ARM (problem with new stub function in the PMU code).
I've fixed up the aspeed i2c patch to deal with the former and
dropped the PMU patches for now.
-- PMM
The following changes since commit 280b2358cd1fc88003773bff3c4d4219f8bd3ae6:
Merge remote-tracking branch 'remotes/gkurz/tags/for-upstream' into staging (2016-06-06 15:17:52 +0100)
are available in the git repository at:
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20160606-1
for you to fetch changes up to 0c18c6c67e06859ef354b697cce567ebe29061f1:
zynqmp: Add the ZCU102 board (2016-06-06 16:59:32 +0100)
----------------------------------------------------------------
target-arm queue:
* support instruction syndrome info for data aborts from A64 to EL2
* add HSTR_EL2 register
* fix incorrect ESR IL bits in various syndrome register cases
* virt: fix limit of 64-bit ACPI/ECAM PCI MMIO range
* gicv2: RAZ/WI non-sec access to sec interrupts
* i2c: add aspeed i2c controller
* virt: Reject gic-version=host for non-KVM (don't segv on aarch64 host)
* xlnx-zynqmp: Add a secure prop to en/disable ARM Security Extensions
* xlnx-zynqmp: Support KVM on AArch64 hosts
* ptimer: Various fixes for awkward corner cases
* char: QOMify various ARM UART models
* char: get rid of qemu_char_get_next_serial
* target-arm: Fix TTBR selecting logic on AArch32 Stage 2 translation
* zynqmp: Add the ZCU102 board
----------------------------------------------------------------
Alistair Francis (2):
target-arm: Add the HSTR_EL2 register
zynqmp: Add the ZCU102 board
Ard Biesheuvel (1):
hw/arm/virt: fix limit of 64-bit ACPI/ECAM PCI MMIO range
Cole Robinson (1):
hw/arm/virt: Reject gic-version=host for non-KVM
Cédric Le Goater (1):
i2c: add aspeed i2c controller
Dmitry Osipenko (5):
hw/ptimer: Fix issues caused by the adjusted timer limit value
hw/ptimer: Perform counter wrap around if timer already expired
hw/ptimer: Update .delta on period/freq change
hw/ptimer: Support "on the fly" timer mode switch
hw/ptimer: Introduce ptimer_get_limit
Edgar E. Iglesias (5):
target-arm: A64: Create Instruction Syndromes for Data Aborts
xlnx-zynqmp: Add a secure prop to en/disable ARM Security Extensions
xlnx-zynqmp: Make the RPU subsystem optional
xlnx-zynqmp: Delay realization of GIC until post CPU realization
xlnx-zynqmp: Use the in kernel GIC model for KVM runs
Jens Wiklander (1):
hw/intc/gic: RAZ/WI non-sec access to sec interrupts
Peter Maydell (2):
target-arm: Set IL bit in syndromes for insn abort, watchpoint, swstep
target-arm: Don't try to set ESR IL bit in arm_cpu_do_interrupt_aarch64()
Sergey Sorokin (1):
target-arm: Fix TTBR selecting logic on AArch32 Stage 2 translation
xiaoqiang zhao (6):
hw/char: QOM'ify pl011 model
hw/char: QOM'ify cadence_uart model
hw/char: QOM'ify digic-uart model
hw/char: QOM'ify stm32f2xx_usart model
hw/char: QOM'ify xilinx_uartlite model
char: get rid of qemu_char_get_next_serial
hw/arm/ast2400.c | 16 ++
hw/arm/bcm2835_peripherals.c | 16 +-
hw/arm/digic.c | 2 +
hw/arm/highbank.c | 3 +-
hw/arm/integratorcp.c | 5 +-
hw/arm/realview.c | 9 +-
hw/arm/stellaris.c | 6 +-
hw/arm/stm32f205_soc.c | 1 +
hw/arm/versatilepb.c | 9 +-
hw/arm/vexpress.c | 9 +-
hw/arm/virt-acpi-build.c | 3 +-
hw/arm/virt.c | 7 +-
hw/arm/xilinx_zynq.c | 5 +-
hw/arm/xlnx-ep108.c | 8 +
hw/arm/xlnx-zynqmp.c | 122 +++++----
hw/char/cadence_uart.c | 13 +-
hw/char/digic-uart.c | 10 +-
hw/char/pl011.c | 11 +-
hw/char/stm32f2xx_usart.c | 15 +-
hw/char/xilinx_uartlite.c | 10 +-
hw/core/ptimer.c | 88 ++++---
hw/i2c/Makefile.objs | 1 +
hw/i2c/aspeed_i2c.c | 440 +++++++++++++++++++++++++++++++
hw/intc/arm_gic.c | 68 ++++-
hw/microblaze/petalogix_s3adsp1800_mmu.c | 5 +-
include/hw/arm/ast2400.h | 2 +
include/hw/arm/xlnx-zynqmp.h | 5 +
include/hw/char/cadence_uart.h | 17 ++
include/hw/char/pl011.h | 52 ++++
include/hw/char/xilinx_uartlite.h | 35 +++
include/hw/i2c/aspeed_i2c.h | 62 +++++
include/hw/ptimer.h | 1 +
include/sysemu/char.h | 1 -
qemu-char.c | 16 --
target-arm/cpu.h | 15 +-
target-arm/helper.c | 48 ++--
target-arm/internals.h | 6 +-
target-arm/op_helper.c | 49 +++-
target-arm/translate-a64.c | 140 ++++++++--
target-arm/translate.c | 5 +-
target-arm/translate.h | 2 +
41 files changed, 1125 insertions(+), 213 deletions(-)
create mode 100644 hw/i2c/aspeed_i2c.c
create mode 100644 include/hw/char/pl011.h
create mode 100644 include/hw/char/xilinx_uartlite.h
create mode 100644 include/hw/i2c/aspeed_i2c.h
next reply other threads:[~2016-06-06 16:02 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-06-06 16:02 Peter Maydell [this message]
2016-06-06 16:38 ` [Qemu-devel] [PULL v2 00/25] target-arm queue Peter Maydell
-- strict thread matches above, loose matches on Subject: below --
2017-06-02 12:04 Peter Maydell
2017-06-02 13:07 ` Peter Maydell
2019-02-15 10:19 Peter Maydell
2019-02-15 11:09 ` Peter Maydell
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