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* [Qemu-devel] [PULL v2 00/25] target-arm queue
@ 2016-06-06 16:02 Peter Maydell
  2016-06-06 16:38 ` Peter Maydell
  0 siblings, 1 reply; 6+ messages in thread
From: Peter Maydell @ 2016-06-06 16:02 UTC (permalink / raw)
  To: qemu-devel

Whoops, v1 didn't build on clang (warning about unused functions)
or 32-bit ARM (problem with new stub function in the PMU code).
I've fixed up the aspeed i2c patch to deal with the former and
dropped the PMU patches for now.

-- PMM


The following changes since commit 280b2358cd1fc88003773bff3c4d4219f8bd3ae6:

  Merge remote-tracking branch 'remotes/gkurz/tags/for-upstream' into staging (2016-06-06 15:17:52 +0100)

are available in the git repository at:


  git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20160606-1

for you to fetch changes up to 0c18c6c67e06859ef354b697cce567ebe29061f1:

  zynqmp: Add the ZCU102 board (2016-06-06 16:59:32 +0100)

----------------------------------------------------------------
target-arm queue:
 * support instruction syndrome info for data aborts from A64 to EL2
 * add HSTR_EL2 register
 * fix incorrect ESR IL bits in various syndrome register cases
 * virt: fix limit of 64-bit ACPI/ECAM PCI MMIO range
 * gicv2: RAZ/WI non-sec access to sec interrupts
 * i2c: add aspeed i2c controller
 * virt: Reject gic-version=host for non-KVM (don't segv on aarch64 host)
 * xlnx-zynqmp: Add a secure prop to en/disable ARM Security Extensions
 * xlnx-zynqmp: Support KVM on AArch64 hosts
 * ptimer: Various fixes for awkward corner cases
 * char: QOMify various ARM UART models
 * char: get rid of qemu_char_get_next_serial
 * target-arm: Fix TTBR selecting logic on AArch32 Stage 2 translation
 * zynqmp: Add the ZCU102 board

----------------------------------------------------------------
Alistair Francis (2):
      target-arm: Add the HSTR_EL2 register
      zynqmp: Add the ZCU102 board

Ard Biesheuvel (1):
      hw/arm/virt: fix limit of 64-bit ACPI/ECAM PCI MMIO range

Cole Robinson (1):
      hw/arm/virt: Reject gic-version=host for non-KVM

Cédric Le Goater (1):
      i2c: add aspeed i2c controller

Dmitry Osipenko (5):
      hw/ptimer: Fix issues caused by the adjusted timer limit value
      hw/ptimer: Perform counter wrap around if timer already expired
      hw/ptimer: Update .delta on period/freq change
      hw/ptimer: Support "on the fly" timer mode switch
      hw/ptimer: Introduce ptimer_get_limit

Edgar E. Iglesias (5):
      target-arm: A64: Create Instruction Syndromes for Data Aborts
      xlnx-zynqmp: Add a secure prop to en/disable ARM Security Extensions
      xlnx-zynqmp: Make the RPU subsystem optional
      xlnx-zynqmp: Delay realization of GIC until post CPU realization
      xlnx-zynqmp: Use the in kernel GIC model for KVM runs

Jens Wiklander (1):
      hw/intc/gic: RAZ/WI non-sec access to sec interrupts

Peter Maydell (2):
      target-arm: Set IL bit in syndromes for insn abort, watchpoint, swstep
      target-arm: Don't try to set ESR IL bit in arm_cpu_do_interrupt_aarch64()

Sergey Sorokin (1):
      target-arm: Fix TTBR selecting logic on AArch32 Stage 2 translation

xiaoqiang zhao (6):
      hw/char: QOM'ify pl011 model
      hw/char: QOM'ify cadence_uart model
      hw/char: QOM'ify digic-uart model
      hw/char: QOM'ify stm32f2xx_usart model
      hw/char: QOM'ify xilinx_uartlite model
      char: get rid of qemu_char_get_next_serial

 hw/arm/ast2400.c                         |  16 ++
 hw/arm/bcm2835_peripherals.c             |  16 +-
 hw/arm/digic.c                           |   2 +
 hw/arm/highbank.c                        |   3 +-
 hw/arm/integratorcp.c                    |   5 +-
 hw/arm/realview.c                        |   9 +-
 hw/arm/stellaris.c                       |   6 +-
 hw/arm/stm32f205_soc.c                   |   1 +
 hw/arm/versatilepb.c                     |   9 +-
 hw/arm/vexpress.c                        |   9 +-
 hw/arm/virt-acpi-build.c                 |   3 +-
 hw/arm/virt.c                            |   7 +-
 hw/arm/xilinx_zynq.c                     |   5 +-
 hw/arm/xlnx-ep108.c                      |   8 +
 hw/arm/xlnx-zynqmp.c                     | 122 +++++----
 hw/char/cadence_uart.c                   |  13 +-
 hw/char/digic-uart.c                     |  10 +-
 hw/char/pl011.c                          |  11 +-
 hw/char/stm32f2xx_usart.c                |  15 +-
 hw/char/xilinx_uartlite.c                |  10 +-
 hw/core/ptimer.c                         |  88 ++++---
 hw/i2c/Makefile.objs                     |   1 +
 hw/i2c/aspeed_i2c.c                      | 440 +++++++++++++++++++++++++++++++
 hw/intc/arm_gic.c                        |  68 ++++-
 hw/microblaze/petalogix_s3adsp1800_mmu.c |   5 +-
 include/hw/arm/ast2400.h                 |   2 +
 include/hw/arm/xlnx-zynqmp.h             |   5 +
 include/hw/char/cadence_uart.h           |  17 ++
 include/hw/char/pl011.h                  |  52 ++++
 include/hw/char/xilinx_uartlite.h        |  35 +++
 include/hw/i2c/aspeed_i2c.h              |  62 +++++
 include/hw/ptimer.h                      |   1 +
 include/sysemu/char.h                    |   1 -
 qemu-char.c                              |  16 --
 target-arm/cpu.h                         |  15 +-
 target-arm/helper.c                      |  48 ++--
 target-arm/internals.h                   |   6 +-
 target-arm/op_helper.c                   |  49 +++-
 target-arm/translate-a64.c               | 140 ++++++++--
 target-arm/translate.c                   |   5 +-
 target-arm/translate.h                   |   2 +
 41 files changed, 1125 insertions(+), 213 deletions(-)
 create mode 100644 hw/i2c/aspeed_i2c.c
 create mode 100644 include/hw/char/pl011.h
 create mode 100644 include/hw/char/xilinx_uartlite.h
 create mode 100644 include/hw/i2c/aspeed_i2c.h

^ permalink raw reply	[flat|nested] 6+ messages in thread
* [Qemu-devel] [PULL v2 00/25] target-arm queue
@ 2017-06-02 12:04 Peter Maydell
  2017-06-02 13:07 ` Peter Maydell
  0 siblings, 1 reply; 6+ messages in thread
From: Peter Maydell @ 2017-06-02 12:04 UTC (permalink / raw)
  To: qemu-devel


Dropped the tmp421 patch and the following patch that
depended on it; no other changes.

thanks
-- PMM

The following changes since commit 43771d5d92312504305c19abe29ec5bfabd55f01:

  Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2017-05-31' into staging (2017-06-01 16:39:16 +0100)

are available in the git repository at:

  git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170602

for you to fetch changes up to c7637c04be257968e6df30de961a6a23a0ac3dd8:

  hw/arm/virt: fdt: generate distance-map when needed (2017-06-02 11:51:49 +0100)

----------------------------------------------------------------
target-arm queue:
 * virt: numa: provide ACPI distance info when needed
 * aspeed: fix i2c controller bugs
 * M profile: support MPU
 * gicv3: fix mishandling of BPR1, VBPR1
 * load_uboot_image: don't assume a full header read
 * libvixl: Correct build failures on NetBSD

----------------------------------------------------------------
Andrew Jones (3):
      load_uboot_image: don't assume a full header read
      hw/arm/virt-acpi-build: build SLIT when needed
      hw/arm/virt: fdt: generate distance-map when needed

Cédric Le Goater (4):
      aspeed/i2c: improve command handling
      aspeed/i2c: handle LAST command under the RX command
      aspeed/i2c: introduce a state machine
      aspeed: add some I2C devices to the Aspeed machines

Kamil Rytarowski (1):
      libvixl: Correct build failures on NetBSD

Michael Davidsaver (4):
      armv7m: Improve "-d mmu" tracing for PMSAv7 MPU
      armv7m: Implement M profile default memory map
      armv7m: Classify faults as MemManage or BusFault
      arm: add MPU support to M profile CPUs

Peter Maydell (12):
      hw/intc/arm_gicv3_cpuif: Fix reset value for VMCR_EL2.VBPR1
      hw/intc/arm_gicv3_cpuif: Don't let BPR be set below its minimum
      hw/intc/arm_gicv3_cpuif: Fix priority masking for NS BPR1
      arm: Use the mmu_idx we're passed in arm_cpu_do_unaligned_access()
      arm: Add support for M profile CPUs having different MMU index semantics
      arm: Use different ARMMMUIdx values for M profile
      arm: Clean up handling of no-MPU PMSA CPUs
      arm: Don't clear ARM_FEATURE_PMSA for no-mpu configs
      arm: Don't let no-MPU PMSA cores write to SCTLR.M
      arm: Remove unnecessary check on cpu->pmsav7_dregion
      arm: All M profile cores are PMSA
      arm: Implement HFNMIENA support for M profile MPU

Wei Huang (1):
      target/arm: clear PMUVER field of AA64DFR0 when vPMU=off

 disas/libvixl/Makefile.objs |   3 +
 target/arm/cpu.h            | 118 ++++++++++++++--
 target/arm/translate.h      |   2 +-
 hw/arm/aspeed.c             |  27 ++++
 hw/arm/virt-acpi-build.c    |   4 +
 hw/arm/virt.c               |  21 +++
 hw/core/loader.c            |   3 +-
 hw/i2c/aspeed_i2c.c         |  65 +++++++--
 hw/intc/arm_gicv3_cpuif.c   |  50 ++++++-
 hw/intc/armv7m_nvic.c       | 104 ++++++++++++++
 target/arm/cpu.c            |  28 +++-
 target/arm/helper.c         | 338 ++++++++++++++++++++++++++++++--------------
 target/arm/machine.c        |   7 +-
 target/arm/op_helper.c      |   3 +-
 target/arm/translate-a64.c  |  18 ++-
 target/arm/translate.c      |  14 +-
 16 files changed, 648 insertions(+), 157 deletions(-)

^ permalink raw reply	[flat|nested] 6+ messages in thread
* [Qemu-devel] [PULL v2 00/25] target-arm queue
@ 2019-02-15 10:19 Peter Maydell
  2019-02-15 11:09 ` Peter Maydell
  0 siblings, 1 reply; 6+ messages in thread
From: Peter Maydell @ 2019-02-15 10:19 UTC (permalink / raw)
  To: qemu-devel

v2: drop a couple of RTH's patches that he wants to rework.

The following changes since commit 0266c739abbed804deabb4ccde2aa449466ac3b4:

  Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-feb-14-2019' into staging (2019-02-14 18:33:00 +0000)

are available in the Git repository at:

  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190215

for you to fetch changes up to 0f8b09b22234460cb5b8766a25066cf6b5f06842:

  gdbstub: Send a reply to the vKill packet. (2019-02-15 09:56:41 +0000)

----------------------------------------------------------------
target-arm queue:
 * gdbstub: Send a reply to the vKill packet
 * Improve codegen for neon min/max and saturating arithmetic
 * Fix a bug in clearing FPSCR exception status bits
 * hw/arm/armsse: Fix miswiring of expansion IRQs
 * hw/intc/armv7m_nvic: Allow byte accesses to SHPR1
 * MAINTAINERS: Remove Peter Crosthwaite from various entries
 * arm: Allow system registers for KVM guests to be changed by QEMU code
 * linux-user: support HWCAP_CPUID which exposes ID registers to user code
 * Fix bug in 128-bit cmpxchg for BE Arm guests
 * Implement (no-op) HACR_EL2
 * Fix CRn to be 14 for PMEVTYPER/PMEVCNTR

----------------------------------------------------------------
Aaron Lindsay OS (1):
      target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR

Alex Bennée (5):
      target/arm: relax permission checks for HWCAP_CPUID registers
      target/arm: expose CPUID registers to userspace
      target/arm: expose MPIDR_EL1 to userspace
      target/arm: expose remaining CPUID registers as RAZ
      linux-user/elfload: enable HWCAP_CPUID for AArch64

Catherine Ho (1):
      target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be

Peter Maydell (5):
      target/arm: Implement HACR_EL2
      arm: Allow system registers for KVM guests to be changed by QEMU code
      MAINTAINERS: Remove Peter Crosthwaite from various entries
      hw/intc/armv7m_nvic: Allow byte accesses to SHPR1
      hw/arm/armsse: Fix miswiring of expansion IRQs

Richard Henderson (12):
      target/arm: Rely on optimization within tcg_gen_gvec_or
      target/arm: Use vector minmax expanders for aarch64
      target/arm: Use vector minmax expanders for aarch32
      target/arm: Use tcg integer min/max primitives for neon
      target/arm: Remove neon min/max helpers
      target/arm: Fix vfp_gdb_get/set_reg vs FPSCR
      target/arm: Fix arm_cpu_dump_state vs FPSCR
      target/arm: Split out flags setting from vfp compares
      target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR]
      target/arm: Split out FPSCR.QC to a vector field
      target/arm: Use vector operations for saturation
      target/arm: Add missing clear_tail calls

Sandra Loosemore (1):
      gdbstub: Send a reply to the vKill packet.

 target/arm/cpu.h           |  50 +++++++++-
 target/arm/helper.h        |  45 ++++++---
 target/arm/translate.h     |   4 +
 gdbstub.c                  |   1 +
 hw/arm/armsse.c            |   2 +-
 hw/intc/armv7m_nvic.c      |   4 +-
 linux-user/elfload.c       |   1 +
 target/arm/helper-a64.c    |   4 +-
 target/arm/helper.c        | 228 ++++++++++++++++++++++++++++++++++++---------
 target/arm/kvm32.c         |  20 +---
 target/arm/kvm64.c         |   2 +
 target/arm/machine.c       |   2 +-
 target/arm/neon_helper.c   |  14 +--
 target/arm/translate-a64.c |  77 ++++++---------
 target/arm/translate-sve.c |   6 +-
 target/arm/translate.c     | 219 ++++++++++++++++++++++++++++++++++---------
 target/arm/vec_helper.c    | 134 +++++++++++++++++++++++++-
 MAINTAINERS                |   4 -
 18 files changed, 622 insertions(+), 195 deletions(-)

^ permalink raw reply	[flat|nested] 6+ messages in thread
end of thread, other threads:[~2019-02-15 11:09 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
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2016-06-06 16:02 [Qemu-devel] [PULL v2 00/25] target-arm queue Peter Maydell
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2017-06-02 12:04 Peter Maydell
2017-06-02 13:07 ` Peter Maydell
2019-02-15 10:19 Peter Maydell
2019-02-15 11:09 ` Peter Maydell

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