From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37319) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b9yR4-0002D0-F5 for qemu-devel@nongnu.org; Mon, 06 Jun 2016 13:35:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1b9yR2-0001NG-7u for qemu-devel@nongnu.org; Mon, 06 Jun 2016 13:35:34 -0400 Received: from mx1.redhat.com ([209.132.183.28]:39972) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b9yR2-0001N5-1x for qemu-devel@nongnu.org; Mon, 06 Jun 2016 13:35:32 -0400 From: Paolo Bonzini Date: Mon, 6 Jun 2016 19:35:13 +0200 Message-Id: <1465234520-11160-5-git-send-email-pbonzini@redhat.com> In-Reply-To: <1465234520-11160-1-git-send-email-pbonzini@redhat.com> References: <1465234520-11160-1-git-send-email-pbonzini@redhat.com> Subject: [Qemu-devel] [PULL 04/11] scsi: esp: check TI buffer index before read/write List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Prasad J Pandit From: Prasad J Pandit The 53C9X Fast SCSI Controller(FSC) comes with internal 16-byte FIFO buffers. One is used to handle commands and other is for information transfer. Three control variables 'ti_rptr', 'ti_wptr' and 'ti_size' are used to control r/w access to the information transfer buffer ti_buf[TI_BUFSZ=16]. In that, 'ti_rptr' is used as read index, where read occurs. 'ti_wptr' is a write index, where write would occur. 'ti_size' indicates total bytes to be read from the buffer. While reading/writing to this buffer, index could exceed its size. Add check to avoid OOB r/w access. Reported-by: Huawei PSIRT Reported-by: Li Qiang Signed-off-by: Prasad J Pandit Message-Id: <1465230883-22303-1-git-send-email-ppandit@redhat.com> Signed-off-by: Paolo Bonzini --- hw/scsi/esp.c | 20 +++++++++----------- 1 file changed, 9 insertions(+), 11 deletions(-) diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c index 591c817..3adb685 100644 --- a/hw/scsi/esp.c +++ b/hw/scsi/esp.c @@ -400,19 +400,17 @@ uint64_t esp_reg_read(ESPState *s, uint32_t saddr) trace_esp_mem_readb(saddr, s->rregs[saddr]); switch (saddr) { case ESP_FIFO: - if (s->ti_size > 0) { + if ((s->rregs[ESP_RSTAT] & STAT_PIO_MASK) == 0) { + /* Data out. */ + qemu_log_mask(LOG_UNIMP, "esp: PIO data read not implemented\n"); + s->rregs[ESP_FIFO] = 0; + esp_raise_irq(s); + } else if (s->ti_rptr < s->ti_wptr) { s->ti_size--; - if ((s->rregs[ESP_RSTAT] & STAT_PIO_MASK) == 0) { - /* Data out. */ - qemu_log_mask(LOG_UNIMP, - "esp: PIO data read not implemented\n"); - s->rregs[ESP_FIFO] = 0; - } else { - s->rregs[ESP_FIFO] = s->ti_buf[s->ti_rptr++]; - } + s->rregs[ESP_FIFO] = s->ti_buf[s->ti_rptr++]; esp_raise_irq(s); } - if (s->ti_size == 0) { + if (s->ti_rptr == s->ti_wptr) { s->ti_rptr = 0; s->ti_wptr = 0; } @@ -456,7 +454,7 @@ void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val) } else { trace_esp_error_fifo_overrun(); } - } else if (s->ti_size == TI_BUFSZ - 1) { + } else if (s->ti_wptr == TI_BUFSZ - 1) { trace_esp_error_fifo_overrun(); } else { s->ti_size++; -- 2.5.5