* [Qemu-devel] [PATCH v5 0/3] Add guest PMU in machine virt @ 2016-06-07 2:46 Shannon Zhao 2016-06-07 2:46 ` [Qemu-devel] [PATCH v5 1/3] target-arm: kvm64: set guest PMUv3 feature bit if supported Shannon Zhao ` (3 more replies) 0 siblings, 4 replies; 5+ messages in thread From: Shannon Zhao @ 2016-06-07 2:46 UTC (permalink / raw) To: qemu-arm, peter.maydell Cc: qemu-devel, drjones, shannon.zhao, peter.huangpeng, zhaoshenglong From: Shannon Zhao <shannon.zhao@linaro.org> KVM-ARM64 supports guest PMU now. This series add the support in machine virt so that guest could use PMU. The ACPI part is tested with below guest kernel patches. https://lkml.org/lkml/2016/4/12/755 Changes since v4: * fix building failure due to kvm_arm_pmu_create() * rebase on master Changes since v3: * if kvm_arm_pmu_create returns a failure, don't create pmu dts node for guest Changes since v2: * address Andrew's comments on PATCH 2, thanks Changes since v1: * rebase on master * Address Andrew's comments, add a macro PPI, fix code style, add cpu_to_le32() Shannon Zhao (3): target-arm: kvm64: set guest PMUv3 feature bit if supported hw/arm/virt: Add PMU node for virt machine hw/arm/virt-acpi-build: Add PMU IRQ number in ACPI table hw/arm/virt-acpi-build.c | 4 ++++ hw/arm/virt.c | 33 +++++++++++++++++++++++++++++++++ include/hw/arm/virt.h | 4 ++++ target-arm/cpu.h | 2 ++ target-arm/kvm32.c | 6 ++++++ target-arm/kvm64.c | 46 ++++++++++++++++++++++++++++++++++++++++++++++ target-arm/kvm_arm.h | 7 +++++++ 7 files changed, 102 insertions(+) -- 2.0.4 ^ permalink raw reply [flat|nested] 5+ messages in thread
* [Qemu-devel] [PATCH v5 1/3] target-arm: kvm64: set guest PMUv3 feature bit if supported 2016-06-07 2:46 [Qemu-devel] [PATCH v5 0/3] Add guest PMU in machine virt Shannon Zhao @ 2016-06-07 2:46 ` Shannon Zhao 2016-06-07 2:46 ` [Qemu-devel] [PATCH v5 2/3] hw/arm/virt: Add PMU node for virt machine Shannon Zhao ` (2 subsequent siblings) 3 siblings, 0 replies; 5+ messages in thread From: Shannon Zhao @ 2016-06-07 2:46 UTC (permalink / raw) To: qemu-arm, peter.maydell Cc: qemu-devel, drjones, shannon.zhao, peter.huangpeng, zhaoshenglong From: Shannon Zhao <shannon.zhao@linaro.org> Check if kvm supports guest PMUv3. If so, set the corresponding feature bit for vcpu. Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Reviewed-by: Andrew Jones <drjones@redhat.com> --- target-arm/cpu.h | 2 ++ target-arm/kvm64.c | 5 +++++ 2 files changed, 7 insertions(+) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 401955f..fa6388f 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -574,6 +574,8 @@ struct ARMCPU { bool powered_off; /* CPU has security extension */ bool has_el3; + /* CPU has PMU (Performance Monitor Unit) */ + bool has_pmu; /* CPU has memory protection unit */ bool has_mpu; diff --git a/target-arm/kvm64.c b/target-arm/kvm64.c index e2a34f6..75383c8 100644 --- a/target-arm/kvm64.c +++ b/target-arm/kvm64.c @@ -461,6 +461,11 @@ int kvm_arch_init_vcpu(CPUState *cs) if (!arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_EL1_32BIT; } + if (kvm_irqchip_in_kernel() && + kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_PMU_V3)) { + cpu->has_pmu = true; + cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_PMU_V3; + } /* Do KVM_ARM_VCPU_INIT ioctl */ ret = kvm_arm_vcpu_init(cs); -- 2.0.4 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* [Qemu-devel] [PATCH v5 2/3] hw/arm/virt: Add PMU node for virt machine 2016-06-07 2:46 [Qemu-devel] [PATCH v5 0/3] Add guest PMU in machine virt Shannon Zhao 2016-06-07 2:46 ` [Qemu-devel] [PATCH v5 1/3] target-arm: kvm64: set guest PMUv3 feature bit if supported Shannon Zhao @ 2016-06-07 2:46 ` Shannon Zhao 2016-06-07 2:46 ` [Qemu-devel] [PATCH v5 3/3] hw/arm/virt-acpi-build: Add PMU IRQ number in ACPI table Shannon Zhao 2016-06-07 10:39 ` [Qemu-devel] [PATCH v5 0/3] Add guest PMU in machine virt Peter Maydell 3 siblings, 0 replies; 5+ messages in thread From: Shannon Zhao @ 2016-06-07 2:46 UTC (permalink / raw) To: qemu-arm, peter.maydell Cc: qemu-devel, drjones, shannon.zhao, peter.huangpeng, zhaoshenglong From: Shannon Zhao <shannon.zhao@linaro.org> Add a virtual PMU device for virt machine while use PPI 7 for PMU overflow interrupt number. Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Reviewed-by: Andrew Jones <drjones@redhat.com> --- hw/arm/virt.c | 33 +++++++++++++++++++++++++++++++++ include/hw/arm/virt.h | 4 ++++ target-arm/kvm32.c | 6 ++++++ target-arm/kvm64.c | 41 +++++++++++++++++++++++++++++++++++++++++ target-arm/kvm_arm.h | 7 +++++++ 5 files changed, 91 insertions(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 8e46137..f5ffe65 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -436,6 +436,37 @@ static void fdt_add_gic_node(VirtBoardInfo *vbi, int type) qemu_fdt_setprop_cell(vbi->fdt, "/intc", "phandle", vbi->gic_phandle); } +static void fdt_add_pmu_nodes(const VirtBoardInfo *vbi, int gictype) +{ + CPUState *cpu; + ARMCPU *armcpu; + uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; + + CPU_FOREACH(cpu) { + armcpu = ARM_CPU(cpu); + if (!armcpu->has_pmu || + !kvm_arm_pmu_create(cpu, PPI(VIRTUAL_PMU_IRQ))) { + return; + } + } + + if (gictype == 2) { + irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, + GIC_FDT_IRQ_PPI_CPU_WIDTH, + (1 << vbi->smp_cpus) - 1); + } + + armcpu = ARM_CPU(qemu_get_cpu(0)); + qemu_fdt_add_subnode(vbi->fdt, "/pmu"); + if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { + const char compat[] = "arm,armv8-pmuv3"; + qemu_fdt_setprop(vbi->fdt, "/pmu", "compatible", + compat, sizeof(compat)); + qemu_fdt_setprop_cells(vbi->fdt, "/pmu", "interrupts", + GIC_FDT_IRQ_TYPE_PPI, VIRTUAL_PMU_IRQ, irqflags); + } +} + static void create_v2m(VirtBoardInfo *vbi, qemu_irq *pic) { int i; @@ -1259,6 +1290,8 @@ static void machvirt_init(MachineState *machine) create_gic(vbi, pic, gic_version, vms->secure); + fdt_add_pmu_nodes(vbi, gic_version); + create_uart(vbi, pic, VIRT_UART, sysmem); if (vms->secure) { diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index 82703d2..9650193 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -41,6 +41,10 @@ #define ARCH_TIMER_NS_EL1_IRQ 14 #define ARCH_TIMER_NS_EL2_IRQ 10 +#define VIRTUAL_PMU_IRQ 7 + +#define PPI(irq) ((irq) + 16) + enum { VIRT_FLASH, VIRT_MEM, diff --git a/target-arm/kvm32.c b/target-arm/kvm32.c index c03e3e5..c35c676 100644 --- a/target-arm/kvm32.c +++ b/target-arm/kvm32.c @@ -522,3 +522,9 @@ bool kvm_arm_hw_debug_active(CPUState *cs) { return false; } + +int kvm_arm_pmu_create(CPUState *cs, int irq) +{ + qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__); + return 0; +} diff --git a/target-arm/kvm64.c b/target-arm/kvm64.c index 75383c8..2d6a310 100644 --- a/target-arm/kvm64.c +++ b/target-arm/kvm64.c @@ -382,6 +382,47 @@ static CPUWatchpoint *find_hw_watchpoint(CPUState *cpu, target_ulong addr) return NULL; } +static bool kvm_arm_pmu_support_ctrl(CPUState *cs, struct kvm_device_attr *attr) +{ + return kvm_vcpu_ioctl(cs, KVM_HAS_DEVICE_ATTR, attr) == 0; +} + +int kvm_arm_pmu_create(CPUState *cs, int irq) +{ + int err; + + struct kvm_device_attr attr = { + .group = KVM_ARM_VCPU_PMU_V3_CTRL, + .addr = (intptr_t)&irq, + .attr = KVM_ARM_VCPU_PMU_V3_IRQ, + .flags = 0, + }; + + if (!kvm_arm_pmu_support_ctrl(cs, &attr)) { + return 0; + } + + err = kvm_vcpu_ioctl(cs, KVM_SET_DEVICE_ATTR, &attr); + if (err < 0) { + fprintf(stderr, "KVM_SET_DEVICE_ATTR failed: %s\n", + strerror(-err)); + abort(); + } + + attr.group = KVM_ARM_VCPU_PMU_V3_CTRL; + attr.attr = KVM_ARM_VCPU_PMU_V3_INIT; + attr.addr = 0; + attr.flags = 0; + + err = kvm_vcpu_ioctl(cs, KVM_SET_DEVICE_ATTR, &attr); + if (err < 0) { + fprintf(stderr, "KVM_SET_DEVICE_ATTR failed: %s\n", + strerror(-err)); + abort(); + } + + return 1; +} static inline void set_feature(uint64_t *features, int feature) { diff --git a/target-arm/kvm_arm.h b/target-arm/kvm_arm.h index 345233c..a419368 100644 --- a/target-arm/kvm_arm.h +++ b/target-arm/kvm_arm.h @@ -194,6 +194,8 @@ int kvm_arm_sync_mpstate_to_qemu(ARMCPU *cpu); int kvm_arm_vgic_probe(void); +int kvm_arm_pmu_create(CPUState *cs, int irq); + #else static inline int kvm_arm_vgic_probe(void) @@ -201,6 +203,11 @@ static inline int kvm_arm_vgic_probe(void) return 0; } +static inline int kvm_arm_pmu_create(CPUState *cs, int irq) +{ + return 0; +} + #endif static inline const char *gic_class_name(void) -- 2.0.4 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* [Qemu-devel] [PATCH v5 3/3] hw/arm/virt-acpi-build: Add PMU IRQ number in ACPI table 2016-06-07 2:46 [Qemu-devel] [PATCH v5 0/3] Add guest PMU in machine virt Shannon Zhao 2016-06-07 2:46 ` [Qemu-devel] [PATCH v5 1/3] target-arm: kvm64: set guest PMUv3 feature bit if supported Shannon Zhao 2016-06-07 2:46 ` [Qemu-devel] [PATCH v5 2/3] hw/arm/virt: Add PMU node for virt machine Shannon Zhao @ 2016-06-07 2:46 ` Shannon Zhao 2016-06-07 10:39 ` [Qemu-devel] [PATCH v5 0/3] Add guest PMU in machine virt Peter Maydell 3 siblings, 0 replies; 5+ messages in thread From: Shannon Zhao @ 2016-06-07 2:46 UTC (permalink / raw) To: qemu-arm, peter.maydell Cc: qemu-devel, drjones, shannon.zhao, peter.huangpeng, zhaoshenglong From: Shannon Zhao <shannon.zhao@linaro.org> Add PMU IRQ number in ACPI table, then we can use PMU in guest through ACPI. Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Reviewed-by: Andrew Jones <drjones@redhat.com> --- hw/arm/virt-acpi-build.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 83a5420..2586769 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -539,6 +539,10 @@ build_madt(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info) gicc->arm_mpidr = armcpu->mp_affinity; gicc->uid = i; gicc->flags = cpu_to_le32(ACPI_GICC_ENABLED); + + if (armcpu->has_pmu) { + gicc->performance_interrupt = cpu_to_le32(PPI(VIRTUAL_PMU_IRQ)); + } } if (guest_info->gic_version == 3) { -- 2.0.4 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [Qemu-devel] [PATCH v5 0/3] Add guest PMU in machine virt 2016-06-07 2:46 [Qemu-devel] [PATCH v5 0/3] Add guest PMU in machine virt Shannon Zhao ` (2 preceding siblings ...) 2016-06-07 2:46 ` [Qemu-devel] [PATCH v5 3/3] hw/arm/virt-acpi-build: Add PMU IRQ number in ACPI table Shannon Zhao @ 2016-06-07 10:39 ` Peter Maydell 3 siblings, 0 replies; 5+ messages in thread From: Peter Maydell @ 2016-06-07 10:39 UTC (permalink / raw) To: Shannon Zhao Cc: qemu-arm, QEMU Developers, Andrew Jones, Shannon Zhao, Huangpeng (Peter) On 7 June 2016 at 03:46, Shannon Zhao <zhaoshenglong@huawei.com> wrote: > From: Shannon Zhao <shannon.zhao@linaro.org> > > KVM-ARM64 supports guest PMU now. This series add the support in machine > virt so that guest could use PMU. > > The ACPI part is tested with below guest kernel patches. > https://lkml.org/lkml/2016/4/12/755 > > Changes since v4: > * fix building failure due to kvm_arm_pmu_create() > * rebase on master > > Changes since v3: > * if kvm_arm_pmu_create returns a failure, don't create pmu dts node for > guest > > Changes since v2: > * address Andrew's comments on PATCH 2, thanks > > Changes since v1: > * rebase on master > * Address Andrew's comments, add a macro PPI, fix code style, add > cpu_to_le32() > > Shannon Zhao (3): > target-arm: kvm64: set guest PMUv3 feature bit if supported > hw/arm/virt: Add PMU node for virt machine > hw/arm/virt-acpi-build: Add PMU IRQ number in ACPI table Applied to target-arm.next, thanks. -- PMM ^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2016-06-07 10:40 UTC | newest] Thread overview: 5+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2016-06-07 2:46 [Qemu-devel] [PATCH v5 0/3] Add guest PMU in machine virt Shannon Zhao 2016-06-07 2:46 ` [Qemu-devel] [PATCH v5 1/3] target-arm: kvm64: set guest PMUv3 feature bit if supported Shannon Zhao 2016-06-07 2:46 ` [Qemu-devel] [PATCH v5 2/3] hw/arm/virt: Add PMU node for virt machine Shannon Zhao 2016-06-07 2:46 ` [Qemu-devel] [PATCH v5 3/3] hw/arm/virt-acpi-build: Add PMU IRQ number in ACPI table Shannon Zhao 2016-06-07 10:39 ` [Qemu-devel] [PATCH v5 0/3] Add guest PMU in machine virt Peter Maydell
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