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From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
To: qemu-ppc@nongnu.org
Cc: qemu-devel@nongnu.org, David Gibson <david@gibson.dropbear.id.au>,
	Cedric Le Goater <clg@kaod.org>,
	Benjamin Herrenschmidt <benh@kernel.crashing.org>
Subject: [Qemu-devel] [PATCH 4/9] ppc: POWER7 had ACOP and PID registers
Date: Tue,  7 Jun 2016 12:50:23 +1000	[thread overview]
Message-ID: <1465267828-10326-4-git-send-email-benh@kernel.crashing.org> (raw)
In-Reply-To: <1465267828-10326-1-git-send-email-benh@kernel.crashing.org>

We only had them on POWER8, add them to POWER7 as well

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
 target-ppc/translate_init.c | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 55f8553..ad6f2f3 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -8024,6 +8024,21 @@ static void gen_spr_power8_book4(CPUPPCState *env)
 #endif
 }
 
+static void gen_spr_power7_book4(CPUPPCState *env)
+{
+    /* Add a number of P7 book4 registers */
+#if !defined(CONFIG_USER_ONLY)
+    spr_register_kvm(env, SPR_ACOP, "ACOP",
+                     SPR_NOACCESS, SPR_NOACCESS,
+                     &spr_read_generic, &spr_write_generic,
+                     KVM_REG_PPC_ACOP, 0);
+    spr_register_kvm(env, SPR_BOOKS_PID, "PID",
+                     SPR_NOACCESS, SPR_NOACCESS,
+                     &spr_read_generic, &spr_write_generic,
+                     KVM_REG_PPC_PID, 0);
+#endif
+}
+
 static void init_proc_book3s_64(CPUPPCState *env, int version)
 {
     gen_spr_ne_601(env);
@@ -8066,6 +8081,9 @@ static void init_proc_book3s_64(CPUPPCState *env, int version)
         gen_spr_power6_common(env);
         gen_spr_power6_dbg(env);
     }
+    if (version == BOOK3S_CPU_POWER7) {
+        gen_spr_power7_book4(env);
+    }
     if (version >= BOOK3S_CPU_POWER8) {
         gen_spr_power8_tce_address_control(env);
         gen_spr_power8_ids(env);
-- 
2.5.5

  parent reply	other threads:[~2016-06-07  3:32 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-06-07  2:50 [Qemu-devel] [PATCH 1/9] ppc: Properly tag the translation cache based on MMU mode Benjamin Herrenschmidt
2016-06-07  2:50 ` [Qemu-devel] [PATCH 2/9] ppc: Fix tlb invalidations on 6xx/7xx/7xxx 32-bit processors Benjamin Herrenschmidt
2016-06-07  2:50 ` [Qemu-devel] [PATCH 3/9] ppc: Batch TLB flushes on 32-bit 6xx/7xx/7xxx in hash mode Benjamin Herrenschmidt
2016-06-07  2:50 ` Benjamin Herrenschmidt [this message]
2016-06-07  2:50 ` [Qemu-devel] [PATCH 5/9] ppc: POWER7 has lq/stq instructions and stq need to check ISA Benjamin Herrenschmidt
2016-06-07  2:50 ` [Qemu-devel] [PATCH 6/9] ppc: Fix mtmsr decoding Benjamin Herrenschmidt
2016-06-07  2:50 ` [Qemu-devel] [PATCH 7/9] ppc: Fix slbia decode Benjamin Herrenschmidt
2016-06-07  2:50 ` [Qemu-devel] [PATCH 8/9] ppc: Add missing slbfee. instruction on ppc64 BookS processors Benjamin Herrenschmidt
2016-07-05 17:23   ` [Qemu-devel] [Qemu-ppc] " Cédric Le Goater
2016-07-05 22:10     ` Benjamin Herrenschmidt
2016-07-06  6:57       ` Cédric Le Goater
2016-07-06  7:24         ` Benjamin Herrenschmidt
2016-07-06  7:53           ` Cédric Le Goater
2016-07-06  8:14             ` Benjamin Herrenschmidt
2016-06-07  2:50 ` [Qemu-devel] [PATCH 9/9] ppc: Do not take exceptions on unknown SPRs in privileged mode Benjamin Herrenschmidt

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