From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48678) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bAJG0-0000tL-8y for qemu-devel@nongnu.org; Tue, 07 Jun 2016 11:49:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bAJFu-0004zf-Us for qemu-devel@nongnu.org; Tue, 07 Jun 2016 11:49:32 -0400 Received: from mail.uni-paderborn.de ([131.234.142.9]:60982) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bAJFu-0004yO-Nu for qemu-devel@nongnu.org; Tue, 07 Jun 2016 11:49:26 -0400 From: peer.adelt@c-lab.de Date: Tue, 7 Jun 2016 17:49:11 +0200 Message-Id: <1465314555-11501-1-git-send-email-peer.adelt@c-lab.de> Subject: [Qemu-devel] [PATCH v3 0/4] Added 5 instructions to the tricore target List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: kbastian@mail.uni-paderborn.de, rth@twiddle.net, Peer Adelt From: Peer Adelt This patch set contains 5 new instructions: - FTOUZ (converts float to unsigned int, rounds towards zero) - MADD.F / MSUB.F (multiplies two floats and adds/subtracts result to/from the third operand) - MOV (new variant in RR format - see ISA v1.6 for details) - JNE (new variant in SBC format - see ISA v1.6 for details) v3: PATCH 1/4: target-tricore: Added FTOUZ instruction - Removed unnecessary cast PATCH 2/4: target-tricore: Added MADD.F and MSUB.F instructions - Provided correct negation options for float32_muladd() instead of negating one of the input arguments - Calculate NaN results as required in the datasheet PATCH 3/4: target-tricore: Added new MOV instruction variant - Removed unnecessary parentheses - Used temp register to avoid losing the value of r1 - Checks that r3+1:r3 for a valid 64 Bit extended register PATCH 4/4: target-tricore: Added new JNE instruction variant - gen_compute_branch() now calculates the displacement value v2: PATCH 3/4: target-tricore: Added new MOV instruction variant - Checks TriCore ISA version requirement PATCH 4/4: target-tricore: Added new JNE instruction variant - Checks TriCore ISA version requirement Peer Adelt (4): target-tricore: Added FTOUZ instruction target-tricore: Added MADD.F and MSUB.F instructions target-tricore: Added new MOV instruction variant target-tricore: Added new JNE instruction variant target-tricore/fpu_helper.c | 77 ++++++++++++++++++++++++++++++++++++++++ target-tricore/helper.h | 3 ++ target-tricore/translate.c | 42 ++++++++++++++++++++++ target-tricore/tricore-opcodes.h | 3 ++ 4 files changed, 125 insertions(+) -- 2.7.4