From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48661) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bAJFy-0000sV-PC for qemu-devel@nongnu.org; Tue, 07 Jun 2016 11:49:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bAJFt-0004yz-Nf for qemu-devel@nongnu.org; Tue, 07 Jun 2016 11:49:30 -0400 Received: from mail.uni-paderborn.de ([131.234.142.9]:60980) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bAJFt-0004yN-GM for qemu-devel@nongnu.org; Tue, 07 Jun 2016 11:49:25 -0400 From: peer.adelt@c-lab.de Date: Tue, 7 Jun 2016 17:49:12 +0200 Message-Id: <1465314555-11501-2-git-send-email-peer.adelt@c-lab.de> In-Reply-To: <1465314555-11501-1-git-send-email-peer.adelt@c-lab.de> References: <1465314555-11501-1-git-send-email-peer.adelt@c-lab.de> Subject: [Qemu-devel] [PATCH v3 1/4] target-tricore: Added FTOUZ instruction List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: kbastian@mail.uni-paderborn.de, rth@twiddle.net, Peer Adelt From: Peer Adelt Converts a 32-bit floating point number to an unsigned int. The result is rounded towards zero. Signed-off-by: Peer Adelt Reviewed-by: Bastian Koppelmann --- target-tricore/fpu_helper.c | 20 ++++++++++++++++++++ target-tricore/helper.h | 1 + target-tricore/translate.c | 3 +++ 3 files changed, 24 insertions(+) diff --git a/target-tricore/fpu_helper.c b/target-tricore/fpu_helper.c index 98fe947..16f274c 100644 --- a/target-tricore/fpu_helper.c +++ b/target-tricore/fpu_helper.c @@ -215,3 +215,23 @@ uint32_t helper_itof(CPUTriCoreState *env, uint32_t arg) } return (uint32_t)f_result; } + +uint32_t helper_ftouz(CPUTriCoreState *env, uint32_t arg) +{ + float32 f_arg = make_float32(arg); + uint32_t result; + int32_t flags; + + result = float32_to_uint32_round_to_zero(f_arg, &env->fp_status); + + flags = f_get_excp_flags(env); + if (flags) { + if (float32_is_any_nan(f_arg)) { + result = 0; + } + f_update_psw_flags(env, flags); + } else { + env->FPU_FS = 0; + } + return result; +} diff --git a/target-tricore/helper.h b/target-tricore/helper.h index 9333e16..467c880 100644 --- a/target-tricore/helper.h +++ b/target-tricore/helper.h @@ -112,6 +112,7 @@ DEF_HELPER_3(fdiv, i32, env, i32, i32) DEF_HELPER_3(fcmp, i32, env, i32, i32) DEF_HELPER_2(ftoi, i32, env, i32) DEF_HELPER_2(itof, i32, env, i32) +DEF_HELPER_2(ftouz, i32, env, i32) /* dvinit */ DEF_HELPER_3(dvinit_b_13, i64, env, i32, i32) DEF_HELPER_3(dvinit_b_131, i64, env, i32, i32) diff --git a/target-tricore/translate.c b/target-tricore/translate.c index eb3deac..b888b64 100644 --- a/target-tricore/translate.c +++ b/target-tricore/translate.c @@ -6698,6 +6698,9 @@ static void decode_rr_divide(CPUTriCoreState *env, DisasContext *ctx) case OPC2_32_RR_ITOF: gen_helper_itof(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]); break; + case OPC2_32_RR_FTOUZ: + gen_helper_ftouz(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]); + break; default: generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); } -- 2.7.4