From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48709) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bAJG2-0000vO-LO for qemu-devel@nongnu.org; Tue, 07 Jun 2016 11:49:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bAJFt-0004zD-ST for qemu-devel@nongnu.org; Tue, 07 Jun 2016 11:49:34 -0400 Received: from mail.uni-paderborn.de ([131.234.142.9]:37917) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bAJFt-0004yY-Ic for qemu-devel@nongnu.org; Tue, 07 Jun 2016 11:49:25 -0400 From: peer.adelt@c-lab.de Date: Tue, 7 Jun 2016 17:49:13 +0200 Message-Id: <1465314555-11501-3-git-send-email-peer.adelt@c-lab.de> In-Reply-To: <1465314555-11501-1-git-send-email-peer.adelt@c-lab.de> References: <1465314555-11501-1-git-send-email-peer.adelt@c-lab.de> Subject: [Qemu-devel] [PATCH v3 2/4] target-tricore: Added MADD.F and MSUB.F instructions List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: kbastian@mail.uni-paderborn.de, rth@twiddle.net, Peer Adelt From: Peer Adelt Multiplies D[a] and D[b] and adds/subtracts the result to/from D[d]. The result is put in D[c]. All operands are floating-point numbers. Signed-off-by: Peer Adelt --- target-tricore/fpu_helper.c | 80 +++++++++++++++++++++++++++++++++++++++++++++ target-tricore/helper.h | 2 ++ target-tricore/translate.c | 8 +++++ 3 files changed, 90 insertions(+) diff --git a/target-tricore/fpu_helper.c b/target-tricore/fpu_helper.c index 16f274c..a4b0973 100644 --- a/target-tricore/fpu_helper.c +++ b/target-tricore/fpu_helper.c @@ -21,6 +21,7 @@ #include "cpu.h" #include "exec/helper-proto.h" +#define QUIET_NAN 0x7fc00000 #define ADD_NAN 0x7cf00001 #define DIV_NAN 0x7fc00008 #define MUL_NAN 0x7fc00002 @@ -47,6 +48,39 @@ static inline bool f_is_denormal(float32 arg) return float32_is_zero_or_denormal(arg) && !float32_is_zero(arg); } +static inline int f_is_pos_infinity(float32 a) +{ + return !float32_is_neg(a) && float32_is_infinity(a); +} + +static inline int f_is_neg_infinity(float32 a) +{ + return float32_is_neg(a) && float32_is_infinity(a); +} + +static inline float32 f_maddsub_nan_result(float32 arg1, float32 arg2, + float32 arg3, float32 result) +{ + if (float32_is_any_nan(arg1) || + float32_is_any_nan(arg2) || + float32_is_any_nan(arg3)) { + return QUIET_NAN; + } else if (float32_is_infinity(arg1) && float32_is_zero(arg2)) { + return MUL_NAN; + } else if (float32_is_zero(arg1) && float32_is_infinity(arg2)) { + return MUL_NAN; + } else if (((f_is_neg_infinity(arg1) && f_is_neg_infinity(arg2)) || + (f_is_pos_infinity(arg1) && f_is_pos_infinity(arg2))) && + f_is_neg_infinity(arg3)) { + return ADD_NAN; + } else if (((f_is_neg_infinity(arg1) && f_is_pos_infinity(arg2)) || + (f_is_pos_infinity(arg1) && f_is_neg_infinity(arg2))) && + f_is_pos_infinity(arg3)) { + return ADD_NAN; + } + return result; +} + static void f_update_psw_flags(CPUTriCoreState *env, uint8_t flags) { uint8_t some_excp = 0; @@ -159,6 +193,52 @@ uint32_t helper_fdiv(CPUTriCoreState *env, uint32_t r1, uint32_t r2) return (uint32_t)f_result; } +uint32_t helper_fmadd(CPUTriCoreState *env, uint32_t r1, + uint32_t r2, uint32_t r3) +{ + uint32_t flags; + float32 arg1 = make_float32(r1); + float32 arg2 = make_float32(r2); + float32 arg3 = make_float32(r3); + float32 f_result; + + f_result = float32_muladd(arg1, arg2, arg3, 0, &env->fp_status); + + flags = f_get_excp_flags(env); + if (flags) { + if (flags & float_flag_invalid) { + f_result = f_maddsub_nan_result(arg1, arg2, arg3, f_result); + } + f_update_psw_flags(env, flags); + } else { + env->FPU_FS = 0; + } + return (uint32_t)f_result; +} + +uint32_t helper_fmsub(CPUTriCoreState *env, uint32_t r1, + uint32_t r2, uint32_t r3) +{ + uint32_t flags; + float32 arg1 = make_float32(r1); + float32 arg2 = make_float32(r2); + float32 arg3 = make_float32(r3); + float32 f_result; + + f_result = float32_muladd(arg1, arg2, arg3, float_muladd_negate_product, &env->fp_status); + + flags = f_get_excp_flags(env); + if (flags) { + if (flags & float_flag_invalid) { + f_result = f_maddsub_nan_result(arg1, arg2, arg3, f_result); + } + f_update_psw_flags(env, flags); + } else { + env->FPU_FS = 0; + } + return (uint32_t)f_result; +} + uint32_t helper_fcmp(CPUTriCoreState *env, uint32_t r1, uint32_t r2) { uint32_t result, flags; diff --git a/target-tricore/helper.h b/target-tricore/helper.h index 467c880..c897a44 100644 --- a/target-tricore/helper.h +++ b/target-tricore/helper.h @@ -109,6 +109,8 @@ DEF_HELPER_3(fadd, i32, env, i32, i32) DEF_HELPER_3(fsub, i32, env, i32, i32) DEF_HELPER_3(fmul, i32, env, i32, i32) DEF_HELPER_3(fdiv, i32, env, i32, i32) +DEF_HELPER_4(fmadd, i32, env, i32, i32, i32) +DEF_HELPER_4(fmsub, i32, env, i32, i32, i32) DEF_HELPER_3(fcmp, i32, env, i32, i32) DEF_HELPER_2(ftoi, i32, env, i32) DEF_HELPER_2(itof, i32, env, i32) diff --git a/target-tricore/translate.c b/target-tricore/translate.c index b888b64..07b0a8b 100644 --- a/target-tricore/translate.c +++ b/target-tricore/translate.c @@ -7096,6 +7096,14 @@ static void decode_rrr_divide(CPUTriCoreState *env, DisasContext *ctx) case OPC2_32_RRR_SUB_F: gen_helper_fsub(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r3]); break; + case OPC2_32_RRR_MADD_F: + gen_helper_fmadd(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], + cpu_gpr_d[r2], cpu_gpr_d[r3]); + break; + case OPC2_32_RRR_MSUB_F: + gen_helper_fmsub(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], + cpu_gpr_d[r2], cpu_gpr_d[r3]); + break; default: generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); } -- 2.7.4