From: Leon Alrae <leon.alrae@imgtec.com>
To: qemu-devel@nongnu.org
Cc: aurelien@aurel32.net
Subject: [Qemu-devel] [PATCH 0/3] mips: support configurable exception vector base
Date: Thu, 9 Jun 2016 10:46:49 +0100 [thread overview]
Message-ID: <1465465612-4543-1-git-send-email-leon.alrae@imgtec.com> (raw)
This series implements the last piece of the minimal support required to
boot MIPSr6 SMP Linux on multiple Virtual Processors. Essentially it adds
RESET_BASE register to CM GCR which can be used by the guest to specify the
reset exception base address for each VP.
It applies on top of GIC patches:
https://lists.nongnu.org/archive/html/qemu-devel/2016-03/msg06223.html
Thanks,
Leon
Leon Alrae (3):
target-mips: add exception base to MIPS CPU
hw/mips_cpc: make VP correctly start from the reset vector
hw/mips_cmgcr: implement RESET_BASE register in CM GCR
hw/misc/mips_cmgcr.c | 54 +++++++++++++++++++++++++++++++++++++++++++-
hw/misc/mips_cpc.c | 5 ++--
include/hw/misc/mips_cmgcr.h | 18 +++++++++++++++
target-mips/cpu.h | 2 ++
target-mips/helper.c | 6 ++---
target-mips/translate.c | 9 +++++++-
6 files changed, 86 insertions(+), 8 deletions(-)
--
2.7.4
next reply other threads:[~2016-06-09 9:47 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-06-09 9:46 Leon Alrae [this message]
2016-06-09 9:46 ` [Qemu-devel] [PATCH 1/3] target-mips: add exception base to MIPS CPU Leon Alrae
2016-06-09 9:46 ` [Qemu-devel] [PATCH 2/3] hw/mips_cpc: make VP correctly start from the reset vector Leon Alrae
2016-06-09 9:46 ` [Qemu-devel] [PATCH 3/3] hw/mips_cmgcr: implement RESET_BASE register in CM GCR Leon Alrae
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