From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53779) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bB3In-0006NK-Sw for qemu-devel@nongnu.org; Thu, 09 Jun 2016 12:59:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bB3Im-00058v-JO for qemu-devel@nongnu.org; Thu, 09 Jun 2016 12:59:29 -0400 Received: from mx1.redhat.com ([209.132.183.28]:53392) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bB3Im-00058i-B0 for qemu-devel@nongnu.org; Thu, 09 Jun 2016 12:59:28 -0400 From: "Daniel P. Berrange" Date: Thu, 9 Jun 2016 17:58:30 +0100 Message-Id: <1465491514-7365-37-git-send-email-berrange@redhat.com> In-Reply-To: <1465491514-7365-1-git-send-email-berrange@redhat.com> References: <1465491514-7365-1-git-send-email-berrange@redhat.com> Subject: [Qemu-devel] [PATCH v1 36/40] trace: split out trace events for target-sparc/ directory List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Stefan Hajnoczi , Peter Maydell , "Daniel P. Berrange" Move all trace-events for files in the target-sparc/ directory to their own file. Signed-off-by: Daniel P. Berrange --- Makefile.objs | 1 + target-sparc/trace-events | 53 +++++++++++++++++++++++++++++++++++++++++++++++ trace-events | 27 ------------------------ 3 files changed, 54 insertions(+), 27 deletions(-) create mode 100644 target-sparc/trace-events diff --git a/Makefile.objs b/Makefile.objs index 22f45b9..16c84c2 100644 --- a/Makefile.objs +++ b/Makefile.objs @@ -153,3 +153,4 @@ trace-events-y += hw/alpha/trace-events trace-events-y += ui/trace-events trace-events-y += audio/trace-events trace-events-y += net/trace-events +trace-events-y += target-sparc/trace-events diff --git a/target-sparc/trace-events b/target-sparc/trace-events new file mode 100644 index 0000000..5c8b21c --- /dev/null +++ b/target-sparc/trace-events @@ -0,0 +1,53 @@ +# Trace events for debugging and performance instrumentation +# +# This file is processed by the tracetool script during the build. +# +# To add a new trace event: +# +# 1. Choose a name for the trace event. Declare its arguments and format +# string. +# +# 2. Call the trace event from code using trace_##name, e.g. multiwrite_cb() -> +# trace_multiwrite_cb(). The source file must #include "trace.h". +# +# Format of a trace event: +# +# [disable] ( [, ] ...) "" +# +# Example: g_malloc(size_t size) "size %zu" +# +# The "disable" keyword will build without the trace event. +# +# The must be a valid as a C function name. +# +# Types should be standard C types. Use void * for pointers because the trace +# system may not have the necessary headers included. +# +# The should be a sprintf()-compatible format string. + +# target-sparc/mmu_helper.c +mmu_helper_dfault(uint64_t address, uint64_t context, int mmu_idx, uint32_t tl) "DFAULT at %"PRIx64" context %"PRIx64" mmu_idx=%d tl=%d" +mmu_helper_dprot(uint64_t address, uint64_t context, int mmu_idx, uint32_t tl) "DPROT at %"PRIx64" context %"PRIx64" mmu_idx=%d tl=%d" +mmu_helper_dmiss(uint64_t address, uint64_t context) "DMISS at %"PRIx64" context %"PRIx64 +mmu_helper_tfault(uint64_t address, uint64_t context) "TFAULT at %"PRIx64" context %"PRIx64 +mmu_helper_tmiss(uint64_t address, uint64_t context) "TMISS at %"PRIx64" context %"PRIx64 +mmu_helper_get_phys_addr_code(uint32_t tl, int mmu_idx, uint64_t prim_context, uint64_t sec_context, uint64_t address) "tl=%d mmu_idx=%d primary context=%"PRIx64" secondary context=%"PRIx64" address=%"PRIx64 +mmu_helper_get_phys_addr_data(uint32_t tl, int mmu_idx, uint64_t prim_context, uint64_t sec_context, uint64_t address) "tl=%d mmu_idx=%d primary context=%"PRIx64" secondary context=%"PRIx64" address=%"PRIx64 +mmu_helper_mmu_fault(uint64_t address, uint64_t paddr, int mmu_idx, uint32_t tl, uint64_t prim_context, uint64_t sec_context) "Translate at %"PRIx64" -> %"PRIx64", mmu_idx=%d tl=%d primary context=%"PRIx64" secondary context=%"PRIx64 + +# target-sparc/int64_helper.c +int_helper_set_softint(uint32_t softint) "new %08x" +int_helper_clear_softint(uint32_t softint) "new %08x" +int_helper_write_softint(uint32_t softint) "new %08x" + +# target-sparc/int32_helper.c +int_helper_icache_freeze(void) "Instruction cache: freeze" +int_helper_dcache_freeze(void) "Data cache: freeze" + +# target-sparc/win_helper.c +win_helper_gregset_error(uint32_t pstate) "ERROR in get_gregset: active pstate bits=%x" +win_helper_switch_pstate(uint32_t pstate_regs, uint32_t new_pstate_regs) "change_pstate: switching regs old=%x new=%x" +win_helper_no_switch_pstate(uint32_t new_pstate_regs) "change_pstate: regs new=%x (unchanged)" +win_helper_wrpil(uint32_t psrpil, uint32_t new_pil) "old=%x new=%x" +win_helper_done(uint32_t tl) "tl=%d" +win_helper_retry(uint32_t tl) "tl=%d" diff --git a/trace-events b/trace-events index e5bc1c9..2a8f1ec 100644 --- a/trace-events +++ b/trace-events @@ -103,33 +103,6 @@ monitor_protocol_event_emit(uint32_t event, void *data) "event=%d data=%p" monitor_protocol_event_queue(uint32_t event, void *qdict, uint64_t rate) "event=%d data=%p rate=%" PRId64 monitor_protocol_event_throttle(uint32_t event, uint64_t rate) "event=%d rate=%" PRId64 -# target-sparc/mmu_helper.c -mmu_helper_dfault(uint64_t address, uint64_t context, int mmu_idx, uint32_t tl) "DFAULT at %"PRIx64" context %"PRIx64" mmu_idx=%d tl=%d" -mmu_helper_dprot(uint64_t address, uint64_t context, int mmu_idx, uint32_t tl) "DPROT at %"PRIx64" context %"PRIx64" mmu_idx=%d tl=%d" -mmu_helper_dmiss(uint64_t address, uint64_t context) "DMISS at %"PRIx64" context %"PRIx64 -mmu_helper_tfault(uint64_t address, uint64_t context) "TFAULT at %"PRIx64" context %"PRIx64 -mmu_helper_tmiss(uint64_t address, uint64_t context) "TMISS at %"PRIx64" context %"PRIx64 -mmu_helper_get_phys_addr_code(uint32_t tl, int mmu_idx, uint64_t prim_context, uint64_t sec_context, uint64_t address) "tl=%d mmu_idx=%d primary context=%"PRIx64" secondary context=%"PRIx64" address=%"PRIx64 -mmu_helper_get_phys_addr_data(uint32_t tl, int mmu_idx, uint64_t prim_context, uint64_t sec_context, uint64_t address) "tl=%d mmu_idx=%d primary context=%"PRIx64" secondary context=%"PRIx64" address=%"PRIx64 -mmu_helper_mmu_fault(uint64_t address, uint64_t paddr, int mmu_idx, uint32_t tl, uint64_t prim_context, uint64_t sec_context) "Translate at %"PRIx64" -> %"PRIx64", mmu_idx=%d tl=%d primary context=%"PRIx64" secondary context=%"PRIx64 - -# target-sparc/int64_helper.c -int_helper_set_softint(uint32_t softint) "new %08x" -int_helper_clear_softint(uint32_t softint) "new %08x" -int_helper_write_softint(uint32_t softint) "new %08x" - -# target-sparc/int32_helper.c -int_helper_icache_freeze(void) "Instruction cache: freeze" -int_helper_dcache_freeze(void) "Data cache: freeze" - -# target-sparc/win_helper.c -win_helper_gregset_error(uint32_t pstate) "ERROR in get_gregset: active pstate bits=%x" -win_helper_switch_pstate(uint32_t pstate_regs, uint32_t new_pstate_regs) "change_pstate: switching regs old=%x new=%x" -win_helper_no_switch_pstate(uint32_t new_pstate_regs) "change_pstate: regs new=%x (unchanged)" -win_helper_wrpil(uint32_t psrpil, uint32_t new_pil) "old=%x new=%x" -win_helper_done(uint32_t tl) "tl=%d" -win_helper_retry(uint32_t tl) "tl=%d" - # dma-helpers.c dma_blk_io(void *dbs, void *bs, int64_t offset, bool to_dev) "dbs=%p bs=%p offset=%" PRId64 " to_dev=%d" dma_aio_cancel(void *dbs) "dbs=%p" -- 2.5.5