From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55867) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bBQQX-0006XT-3f for qemu-devel@nongnu.org; Fri, 10 Jun 2016 13:41:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bBQQV-0000Rk-RI for qemu-devel@nongnu.org; Fri, 10 Jun 2016 13:41:01 -0400 From: Andrew Jones Date: Fri, 10 Jun 2016 19:40:18 +0200 Message-Id: <1465580427-13596-8-git-send-email-drjones@redhat.com> In-Reply-To: <1465580427-13596-1-git-send-email-drjones@redhat.com> References: <1465580427-13596-1-git-send-email-drjones@redhat.com> Subject: [Qemu-devel] [PATCH RFC 07/16] qom/cpu: make nr-cores, nr-threads real properties List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org Cc: imammedo@redhat.com, ehabkost@redhat.com, pbonzini@redhat.com, peter.maydell@linaro.org, david@gibson.dropbear.id.au, dgibson@redhat.com, agraf@suse.de Signed-off-by: Andrew Jones --- qom/cpu.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/qom/cpu.c b/qom/cpu.c index 751e992de8823..024cda3eb98c8 100644 --- a/qom/cpu.c +++ b/qom/cpu.c @@ -28,6 +28,7 @@ #include "exec/log.h" #include "qemu/error-report.h" #include "sysemu/sysemu.h" +#include "hw/qdev-properties.h" bool cpu_exists(int64_t id) { @@ -342,6 +343,12 @@ static int64_t cpu_common_get_arch_id(CPUState *cpu) return cpu->cpu_index; } +static Property cpu_common_properties[] = { + DEFINE_PROP_INT32("nr-cores", CPUState, nr_cores, 1), + DEFINE_PROP_INT32("nr-threads", CPUState, nr_threads, 1), + DEFINE_PROP_END_OF_LIST() +}; + static void cpu_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); @@ -367,6 +374,7 @@ static void cpu_class_init(ObjectClass *klass, void *data) k->cpu_exec_exit = cpu_common_noop; k->cpu_exec_interrupt = cpu_common_exec_interrupt; dc->realize = cpu_common_realizefn; + dc->props = cpu_common_properties; /* * Reason: CPUs still need special care by board code: wiring up * IRQs, adding reset handlers, halting non-first CPUs, ... -- 2.4.11