From: Michael Rolnik <mrolnik@gmail.com>
To: qemu-devel@nongnu.org
Cc: rth@twiddle.net, peter.maydell@linaro.org,
Michael Rolnik <mrolnik@gmail.com>
Subject: [Qemu-devel] [PATCH v6 10/11] target-avr: saving sreg, rampD, rampX, rampY, rampD, eind in HW representation saving cpu features
Date: Sun, 12 Jun 2016 22:01:50 +0300 [thread overview]
Message-ID: <1465758111-60131-11-git-send-email-mrolnik@gmail.com> (raw)
In-Reply-To: <1465758111-60131-1-git-send-email-mrolnik@gmail.com>
From: Michael Rolnik <rolnik@amazon.com>
Signed-off-by: Michael Rolnik <mrolnik@gmail.com>
---
target-avr/machine.c | 105 ++++++++++++++++++++++++++++++++++++++++-----------
1 file changed, 84 insertions(+), 21 deletions(-)
diff --git a/target-avr/machine.c b/target-avr/machine.c
index 39f1ee6..9659c04 100644
--- a/target-avr/machine.c
+++ b/target-avr/machine.c
@@ -23,31 +23,94 @@
#include "cpu.h"
#include "hw/boards.h"
#include "machine.h"
+#include "migration/qemu-file.h"
+
+static int get_sreg(QEMUFile *f, void *opaque, size_t size)
+{
+ CPUAVRState* env = opaque;
+ uint8_t sreg;
+
+ qemu_get_8s(f, &sreg);
+ cpu_set_sreg(env, sreg);
+ return 0;
+}
+
+static void put_sreg(QEMUFile *f, void *opaque, size_t size)
+{
+ CPUAVRState* env = opaque;
+ uint8_t sreg = cpu_get_sreg(env);
+
+ qemu_put_8s(f, &sreg);
+}
+
+static const VMStateInfo vmstate_sreg = {
+ .name = "sreg",
+ .get = get_sreg,
+ .put = put_sreg,
+};
+
+static int get_segment(QEMUFile *f, void *opaque, size_t size)
+{
+ uint32_t *ramp = opaque;
+ uint8_t temp = *ramp >> 16;
+
+ qemu_get_8s(f, &temp);
+ return 0;
+}
+
+static void put_segment(QEMUFile *f, void *opaque, size_t size)
+{
+ uint32_t *ramp = opaque;
+ uint8_t temp;
+
+ qemu_put_8s(f, &temp);
+ *ramp = ((uint32_t)temp) << 16;
+}
+
+static const VMStateInfo vmstate_rampD = {
+ .name = "rampD",
+ .get = get_segment,
+ .put = put_segment,
+};
+static const VMStateInfo vmstate_rampX = {
+ .name = "rampX",
+ .get = get_segment,
+ .put = put_segment,
+};
+static const VMStateInfo vmstate_rampY = {
+ .name = "rampY",
+ .get = get_segment,
+ .put = put_segment,
+};
+static const VMStateInfo vmstate_rampZ = {
+ .name = "rampZ",
+ .get = get_segment,
+ .put = put_segment,
+};
+static const VMStateInfo vmstate_eind = {
+ .name = "eind",
+ .get = get_segment,
+ .put = put_segment,
+};
const VMStateDescription vmstate_avr_cpu = {
.name = "cpu",
- .version_id = 1,
- .minimum_version_id = 1,
+ .version_id = 0,
+ .minimum_version_id = 0,
.fields = (VMStateField[]) {
- VMSTATE_UINT32_ARRAY(r, CPUAVRState, 32),
-
- VMSTATE_UINT32(sregC, CPUAVRState),
- VMSTATE_UINT32(sregZ, CPUAVRState),
- VMSTATE_UINT32(sregN, CPUAVRState),
- VMSTATE_UINT32(sregV, CPUAVRState),
- VMSTATE_UINT32(sregS, CPUAVRState),
- VMSTATE_UINT32(sregH, CPUAVRState),
- VMSTATE_UINT32(sregT, CPUAVRState),
- VMSTATE_UINT32(sregI, CPUAVRState),
-
- VMSTATE_UINT32(rampD, CPUAVRState),
- VMSTATE_UINT32(rampX, CPUAVRState),
- VMSTATE_UINT32(rampY, CPUAVRState),
- VMSTATE_UINT32(rampZ, CPUAVRState),
-
- VMSTATE_UINT32(eind, CPUAVRState),
- VMSTATE_UINT32(sp, CPUAVRState),
- VMSTATE_UINT32(pc_w, CPUAVRState),
+ VMSTATE_UINT32(env.features, AVRCPU),
+ VMSTATE_UINT32(env.pc_w, AVRCPU),
+ VMSTATE_UINT32(env.sp, AVRCPU),
+
+ VMSTATE_UINT32_ARRAY(env.r, AVRCPU, 32),
+ VMSTATE_UINT32_ARRAY(env.io, AVRCPU, 64),
+
+ VMSTATE_SINGLE_TEST(env, AVRCPU, NULL, 0, vmstate_sreg, CPUAVRState),
+ VMSTATE_SINGLE_TEST(env.rampD, AVRCPU, NULL, 0, vmstate_rampD, uint32_t),
+ VMSTATE_SINGLE_TEST(env.rampX, AVRCPU, NULL, 0, vmstate_rampX, uint32_t),
+ VMSTATE_SINGLE_TEST(env.rampY, AVRCPU, NULL, 0, vmstate_rampY, uint32_t),
+ VMSTATE_SINGLE_TEST(env.rampZ, AVRCPU, NULL, 0, vmstate_rampZ, uint32_t),
+ VMSTATE_SINGLE_TEST(env.eind, AVRCPU, NULL, 0, vmstate_eind, uint32_t),
VMSTATE_END_OF_LIST()
}
--
2.4.9 (Apple Git-60)
next prev parent reply other threads:[~2016-06-12 19:02 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-06-12 19:01 [Qemu-devel] [PATCH v6 00/11] 8bit AVR cores Michael Rolnik
2016-06-12 19:01 ` [Qemu-devel] [PATCH v6 01/11] target-avr: AVR cores support is added. 1. basic CPU structure 2. registers 3. no instructions Michael Rolnik
2016-06-12 19:01 ` [Qemu-devel] [PATCH v6 02/11] target-avr: adding AVR CPU features/flavors Michael Rolnik
2016-06-12 19:01 ` [Qemu-devel] [PATCH v6 03/11] target-avr: adding a sample AVR board Michael Rolnik
2016-06-12 19:01 ` [Qemu-devel] [PATCH v6 04/11] target-avr: adding instructions encodings Michael Rolnik
2016-06-12 19:01 ` [Qemu-devel] [PATCH v6 05/11] target-avr: adding AVR interrupt handling Michael Rolnik
2016-06-12 19:01 ` [Qemu-devel] [PATCH v6 06/11] target-avr: adding helpers for IN, OUT, SLEEP, WBR & unsupported instructions Michael Rolnik
2016-06-12 19:01 ` [Qemu-devel] [PATCH v6 07/11] target-avr: adding instruction decoder Michael Rolnik
2016-06-12 19:01 ` [Qemu-devel] [PATCH v6 08/11] target-avr: adding instruction translation Michael Rolnik
2016-06-13 16:06 ` Richard Henderson
2016-06-13 20:25 ` Michael Rolnik
2016-06-13 21:31 ` Richard Henderson
2016-06-12 19:01 ` [Qemu-devel] [PATCH v6 09/11] target-avr: updating translate.c to use instructions translation Michael Rolnik
2016-06-13 16:08 ` Richard Henderson
2016-06-12 19:01 ` Michael Rolnik [this message]
2016-06-12 19:01 ` [Qemu-devel] [PATCH v6 11/11] target-avr: decoder generator. currently not used by the build, can be used manually Michael Rolnik
2016-06-13 16:12 ` [Qemu-devel] [PATCH v6 00/11] 8bit AVR cores Richard Henderson
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