From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48422) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bCRdZ-00087Z-TM for qemu-devel@nongnu.org; Mon, 13 Jun 2016 09:10:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bCRdT-0008TN-Md for qemu-devel@nongnu.org; Mon, 13 Jun 2016 09:10:41 -0400 Received: from mx1.redhat.com ([209.132.183.28]:37705) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bCRdT-0008TG-8q for qemu-devel@nongnu.org; Mon, 13 Jun 2016 09:10:35 -0400 From: Peter Xu Date: Mon, 13 Jun 2016 21:09:23 +0800 Message-Id: <1465823381-23602-8-git-send-email-peterx@redhat.com> In-Reply-To: <1465823381-23602-1-git-send-email-peterx@redhat.com> References: <1465823381-23602-1-git-send-email-peterx@redhat.com> Subject: [Qemu-devel] [PATCH v9 07/25] intel_iommu: set IR bit for ECAP register List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: imammedo@redhat.com, rth@twiddle.net, ehabkost@redhat.com, jasowang@redhat.com, marcel@redhat.com, mst@redhat.com, pbonzini@redhat.com, jan.kiszka@web.de, rkrcmar@redhat.com, alex.williamson@redhat.com, wexu@redhat.com, davidkiarie4@gmail.com, peterx@redhat.com Enable IR in IOMMU Extended Capability register. Signed-off-by: Peter Xu --- hw/i386/intel_iommu.c | 6 ++++++ hw/i386/intel_iommu_internal.h | 2 ++ 2 files changed, 8 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index b170f97..e216fd3 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -1948,6 +1948,8 @@ static AddressSpace *vtd_find_add_as(X86IOMMUState *x86_iommu, PCIBus *bus, */ static void vtd_init(IntelIOMMUState *s) { + X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(s); + memset(s->csr, 0, DMAR_REG_SIZE); memset(s->wmask, 0, DMAR_REG_SIZE); memset(s->w1cmask, 0, DMAR_REG_SIZE); @@ -1968,6 +1970,10 @@ static void vtd_init(IntelIOMMUState *s) VTD_CAP_SAGAW | VTD_CAP_MAMV | VTD_CAP_PSI | VTD_CAP_SLLPS; s->ecap = VTD_ECAP_QI | VTD_ECAP_IRO; + if (x86_iommu->intr_supported) { + s->ecap |= VTD_ECAP_IR; + } + vtd_reset_context_cache(s); vtd_reset_iotlb(s); diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index b648e69..5b98a11 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -176,6 +176,8 @@ /* (offset >> 4) << 8 */ #define VTD_ECAP_IRO (DMAR_IOTLB_REG_OFFSET << 4) #define VTD_ECAP_QI (1ULL << 1) +/* Interrupt Remapping support */ +#define VTD_ECAP_IR (1ULL << 3) /* CAP_REG */ /* (offset >> 4) << 24 */ -- 2.4.11