From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49731) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bCvQi-00080X-Fm for qemu-devel@nongnu.org; Tue, 14 Jun 2016 16:59:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bCvQh-0007fq-9G for qemu-devel@nongnu.org; Tue, 14 Jun 2016 16:59:24 -0400 Received: from mx1.redhat.com ([209.132.183.28]:48804) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bCvQh-0007fm-0o for qemu-devel@nongnu.org; Tue, 14 Jun 2016 16:59:23 -0400 From: Eduardo Habkost Date: Tue, 14 Jun 2016 17:59:01 -0300 Message-Id: <1465937948-548-4-git-send-email-ehabkost@redhat.com> In-Reply-To: <1465937948-548-1-git-send-email-ehabkost@redhat.com> References: <1465937948-548-1-git-send-email-ehabkost@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PULL 03/10] target-i386: Implement CPUID[0xB] (Extended Topology Enumeration) List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: =?UTF-8?q?Andreas=20F=C3=A4rber?= , qemu-devel@nongnu.org, Richard Henderson , Paolo Bonzini , =?UTF-8?q?Radim=20Kr=C4=8Dm=C3=A1=C5=99?= From: Radim Kr=C4=8Dm=C3=A1=C5=99 I looked at a dozen Intel CPU that have this CPUID and all of them always had Core offset as 1 (a wasted bit when hyperthreading is disabled) and Package offset at least 4 (wasted bits at <=3D 4 cores). QEMU uses more compact IDs and it doesn't make much sense to change it now. I keep the SMT and Core sub-leaves even if there is just one thread/core; it makes the code simpler and there should be no harm. Signed-off-by: Radim Kr=C4=8Dm=C3=A1=C5=99 Reviewed-by: Eduardo Habkost Signed-off-by: Eduardo Habkost --- include/hw/i386/pc.h | 7 ++++++- target-i386/cpu.c | 32 ++++++++++++++++++++++++++++++++ target-i386/cpu.h | 8 ++++++++ 3 files changed, 46 insertions(+), 1 deletion(-) diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index ca23609..49566c8 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -357,7 +357,12 @@ int e820_get_num_entries(void); bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *); =20 #define PC_COMPAT_2_6 \ - HW_COMPAT_2_6 + HW_COMPAT_2_6 \ + {\ + .driver =3D TYPE_X86_CPU,\ + .property =3D "cpuid-0xb",\ + .value =3D "off",\ + }, =20 #define PC_COMPAT_2_5 \ PC_COMPAT_2_6 \ diff --git a/target-i386/cpu.c b/target-i386/cpu.c index 9c5aabc..f3f95cd 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -41,6 +41,7 @@ =20 #include "sysemu/sysemu.h" #include "hw/qdev-properties.h" +#include "hw/i386/topology.h" #ifndef CONFIG_USER_ONLY #include "exec/address-spaces.h" #include "hw/hw.h" @@ -2492,6 +2493,36 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t inde= x, uint32_t count, *edx =3D 0; } break; + case 0xB: + /* Extended Topology Enumeration Leaf */ + if (!cpu->enable_cpuid_0xb) { + *eax =3D *ebx =3D *ecx =3D *edx =3D 0; + break; + } + + *ecx =3D count & 0xff; + *edx =3D cpu->apic_id; + + switch (count) { + case 0: + *eax =3D apicid_core_offset(smp_cores, smp_threads); + *ebx =3D smp_threads; + *ecx |=3D CPUID_TOPOLOGY_LEVEL_SMT; + break; + case 1: + *eax =3D apicid_pkg_offset(smp_cores, smp_threads); + *ebx =3D smp_cores * smp_threads; + *ecx |=3D CPUID_TOPOLOGY_LEVEL_CORE; + break; + default: + *eax =3D 0; + *ebx =3D 0; + *ecx |=3D CPUID_TOPOLOGY_LEVEL_INVALID; + } + + assert(!(*eax & ~0x1f)); + *ebx &=3D 0xffff; /* The count doesn't need to be reliable. */ + break; case 0xD: { KVMState *s =3D cs->kvm_state; uint64_t ena_mask; @@ -3251,6 +3282,7 @@ static Property x86_cpu_properties[] =3D { DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, 0), DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, 0), DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor_id), + DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true), DEFINE_PROP_END_OF_LIST() }; =20 diff --git a/target-i386/cpu.h b/target-i386/cpu.h index 0426459..d9ab884 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -636,6 +636,11 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_MWAIT_IBE (1U << 1) /* Interrupts can exit capability = */ #define CPUID_MWAIT_EMX (1U << 0) /* enumeration supported */ =20 +/* CPUID[0xB].ECX level types */ +#define CPUID_TOPOLOGY_LEVEL_INVALID (0U << 8) +#define CPUID_TOPOLOGY_LEVEL_SMT (1U << 8) +#define CPUID_TOPOLOGY_LEVEL_CORE (2U << 8) + #ifndef HYPERV_SPINLOCK_NEVER_RETRY #define HYPERV_SPINLOCK_NEVER_RETRY 0xFFFFFFFF #endif @@ -1173,6 +1178,9 @@ struct X86CPU { */ bool enable_pmu; =20 + /* Compatibility bits for old machine types: */ + bool enable_cpuid_0xb; + /* in order to simplify APIC support, we leave this pointer to the user */ struct DeviceState *apic_state; --=20 2.5.5