From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45913) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bDr9k-0004pz-Sv for qemu-devel@nongnu.org; Fri, 17 Jun 2016 06:37:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bDr9b-0004Ys-Fg for qemu-devel@nongnu.org; Fri, 17 Jun 2016 06:37:44 -0400 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:15534 helo=mx0a-001b2d01.pphosted.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bDr9b-0004Y6-BD for qemu-devel@nongnu.org; Fri, 17 Jun 2016 06:37:35 -0400 Received: from pps.filterd (m0098420.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.11/8.16.0.11) with SMTP id u5HATOUj105913 for ; Fri, 17 Jun 2016 06:37:33 -0400 Received: from e36.co.us.ibm.com (e36.co.us.ibm.com [32.97.110.154]) by mx0b-001b2d01.pphosted.com with ESMTP id 23kdg6k9gx-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Fri, 17 Jun 2016 06:37:33 -0400 Received: from localhost by e36.co.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Fri, 17 Jun 2016 04:37:32 -0600 From: "Aneesh Kumar K.V" Date: Fri, 17 Jun 2016 16:07:20 +0530 Message-Id: <1466159840-22141-1-git-send-email-aneesh.kumar@linux.vnet.ibm.com> Subject: [Qemu-devel] [PATCH] powerpc/mm: Update the WIMG check during H_ENTER List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: david@gibson.dropbear.id.au, paulus@samba.org Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, "Aneesh Kumar K.V" Support for 0 value for memeory coherence is optional and with ppc64 we can always enable memory coherence. Linux kernel did that during the development of 4.7 kernel. But that resulted in failure in Qemu in H_ENTER hcall due to below check. The mentioned change was reverted in the kernel and kernel right now enable memory coherence only if cache inhibited is not set. Nevertheless update qemu WIMG flag check to cover the case where we enable memory coherence along with cache inhibited flag. In order to handle older and newer kernel version consider both Cache inhibitted and (cache inhibitted | memory conference) as valid values for wimg flags. Signed-off-by: Aneesh Kumar K.V --- hw/ppc/spapr_hcall.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c index 2ba5cbdb194a..e011ed4b664b 100644 --- a/hw/ppc/spapr_hcall.c +++ b/hw/ppc/spapr_hcall.c @@ -102,11 +102,15 @@ static target_ulong h_enter(PowerPCCPU *cpu, sPAPRMachineState *spapr, return H_PARAMETER; } } else { + target_ulong wimg_flags; /* Looks like an IO address */ /* FIXME: What WIMG combinations could be sensible for IO? * For now we allow WIMG=010x, but are there others? */ /* FIXME: Should we check against registered IO addresses? */ - if ((ptel & (HPTE64_R_W | HPTE64_R_I | HPTE64_R_M)) != HPTE64_R_I) { + wimg_flags = (ptel & (HPTE64_R_W | HPTE64_R_I | HPTE64_R_M)); + + if (wimg_flags != HPTE64_R_I && + wimg_flags != (HPTE64_R_I | HPTE64_R_M)) { return H_PARAMETER; } } -- 2.7.4