From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 05/22] target-arm: Add mp-affinity property for ARM CPU class
Date: Fri, 17 Jun 2016 15:25:35 +0100 [thread overview]
Message-ID: <1466173552-25482-6-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1466173552-25482-1-git-send-email-peter.maydell@linaro.org>
From: Pavel Fedin <p.fedin@samsung.com>
This allows to override default affinity IDs on a per-machine basis, and
possibility to retrieve IDs will be used by vGICv3 live migration code.
Signed-off-by: Pavel Fedin <p.fedin@samsung.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org>
Tested-by: Shannon Zhao <shannon.zhao@linaro.org>
Message-id: 1465915112-29272-6-git-send-email-peter.maydell@linaro.org
---
target-arm/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 0eaa907..ce8b8f4 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -1415,6 +1415,7 @@ static Property arm_cpu_properties[] = {
DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false),
DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0),
DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0),
+ DEFINE_PROP_UINT64("mp-affinity", ARMCPU, mp_affinity, 0),
DEFINE_PROP_END_OF_LIST()
};
--
1.9.1
next prev parent reply other threads:[~2016-06-17 14:26 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-06-17 14:25 [Qemu-devel] [PULL 00/22] target-arm queue Peter Maydell
2016-06-17 14:25 ` [Qemu-devel] [PULL 01/22] migration: Define VMSTATE_UINT64_2DARRAY Peter Maydell
2016-06-17 14:25 ` [Qemu-devel] [PULL 02/22] bitops.h: Implement half-shuffle and half-unshuffle ops Peter Maydell
2016-06-17 14:25 ` [Qemu-devel] [PULL 03/22] target-arm: Define new arm_is_el3_or_mon() function Peter Maydell
2016-06-17 14:25 ` [Qemu-devel] [PULL 04/22] target-arm: Provide hook to tell GICv3 about changes of security state Peter Maydell
2016-06-17 14:25 ` Peter Maydell [this message]
2016-06-17 14:25 ` [Qemu-devel] [PULL 06/22] hw/intc/arm_gicv3: Add state information Peter Maydell
2016-06-17 14:25 ` [Qemu-devel] [PULL 07/22] hw/intc/arm_gicv3: Move irq lines into GICv3CPUState structure Peter Maydell
2016-06-17 14:25 ` [Qemu-devel] [PULL 08/22] hw/intc/arm_gicv3: Add vmstate descriptors Peter Maydell
2016-06-17 14:25 ` [Qemu-devel] [PULL 09/22] hw/intc/arm_gicv3: ARM GICv3 device framework Peter Maydell
2016-06-17 14:25 ` [Qemu-devel] [PULL 10/22] hw/intc/arm_gicv3: Implement functions to identify next pending irq Peter Maydell
2016-06-17 14:25 ` [Qemu-devel] [PULL 11/22] hw/intc/arm_gicv3: Implement GICv3 distributor registers Peter Maydell
2016-06-17 14:25 ` [Qemu-devel] [PULL 12/22] hw/intc/arm_gicv3: Implement GICv3 redistributor registers Peter Maydell
2016-06-17 14:25 ` [Qemu-devel] [PULL 13/22] hw/intc/arm_gicv3: Wire up distributor and redistributor MMIO regions Peter Maydell
2016-06-17 14:25 ` [Qemu-devel] [PULL 14/22] hw/intc/arm_gicv3: Implement gicv3_set_irq() Peter Maydell
2016-06-17 14:25 ` [Qemu-devel] [PULL 15/22] hw/intc/arm_gicv3: Implement GICv3 CPU interface registers Peter Maydell
2016-06-17 14:25 ` [Qemu-devel] [PULL 16/22] hw/intc/arm_gicv3: Implement gicv3_cpuif_update() Peter Maydell
2016-06-17 14:25 ` [Qemu-devel] [PULL 17/22] hw/intc/arm_gicv3: Implement CPU i/f SGI generation registers Peter Maydell
2016-06-17 14:25 ` [Qemu-devel] [PULL 18/22] hw/intc/arm_gicv3: Add IRQ handling CPU interface registers Peter Maydell
2016-06-17 14:25 ` [Qemu-devel] [PULL 19/22] target-arm/machine.c: Allow user to request GICv3 emulation Peter Maydell
2016-06-17 14:25 ` [Qemu-devel] [PULL 20/22] target-arm/monitor.c: Advertise emulated GICv3 in capabilities Peter Maydell
2016-06-17 14:25 ` [Qemu-devel] [PULL 21/22] hw/timer: Add value matching support to aspeed_timer Peter Maydell
2016-06-17 14:25 ` [Qemu-devel] [PULL 22/22] ACPI: ARM: Present GIC version in MADT table Peter Maydell
2016-06-17 16:06 ` [Qemu-devel] [PULL 00/22] target-arm queue Peter Maydell
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