From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50389) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bFQsp-00048N-J2 for qemu-devel@nongnu.org; Tue, 21 Jun 2016 14:58:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bFQso-0008Va-NQ for qemu-devel@nongnu.org; Tue, 21 Jun 2016 14:58:47 -0400 From: Andrew Jones Date: Tue, 21 Jun 2016 20:58:35 +0200 Message-Id: <1466535515-18092-1-git-send-email-drjones@redhat.com> Subject: [Qemu-devel] [PATCH] hw/arm/virt: gicv3: use all target-list bits List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: peter.maydell@linaro.org Signed-off-by: Andrew Jones --- hw/arm/virt.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index c5c125e9204a0..53f545921003c 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1271,6 +1271,16 @@ static void machvirt_init(MachineState *machine) } cpuobj = object_new(object_class_get_name(oc)); + /* Adjust MPIDR per the GIC's target-list size. */ + if (gic_version == 3) { + CPUState *cs = CPU(cpuobj); + uint8_t Aff1 = cs->cpu_index / 16; + uint8_t Aff0 = cs->cpu_index % 16; + + object_property_set_int(cpuobj, (Aff1 << ARM_AFF1_SHIFT) | Aff0, + "mp-affinity", NULL); + } + /* Handle any CPU options specified by the user */ cc->parse_features(CPU(cpuobj), cpuopts, &err); g_free(cpuopts); -- 2.4.11