From: "Cédric Le Goater" <clg@kaod.org>
To: qemu-ppc@nongnu.org
Cc: David Gibson <david@gibson.dropbear.id.au>,
Alexander Graf <agraf@suse.de>,
qemu-devel@nongnu.org,
Benjamin Herrenschmidt <benh@kernel.crashing.org>,
Cedric Le Goater <clg@kaod.org>
Subject: [Qemu-devel] [PATCH v2 08/10] ppc: Turn a bunch of booleans from int to bool
Date: Tue, 21 Jun 2016 23:48:53 +0200 [thread overview]
Message-ID: <1466545735-2555-9-git-send-email-clg@kaod.org> (raw)
In-Reply-To: <1466545735-2555-1-git-send-email-clg@kaod.org>
From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target-ppc/translate.c | 37 ++++++++++++++++++-------------------
1 file changed, 18 insertions(+), 19 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index ca7036b22678..83ec2dd7707b 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -192,22 +192,21 @@ struct DisasContext {
uint32_t opcode;
uint32_t exception;
/* Routine used to access memory */
- bool pr, hv, dr;
+ bool pr, hv, dr, le_mode;
bool lazy_tlb_flush;
int mem_idx;
int access_type;
/* Translation flags */
- int le_mode;
TCGMemOp default_tcg_memop_mask;
#if defined(TARGET_PPC64)
- int sf_mode;
- int has_cfar;
+ bool sf_mode;
+ bool has_cfar;
#endif
- int fpu_enabled;
- int altivec_enabled;
- int vsx_enabled;
- int spe_enabled;
- int tm_enabled;
+ bool fpu_enabled;
+ bool altivec_enabled;
+ bool vsx_enabled;
+ bool spe_enabled;
+ bool tm_enabled;
ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
int singlestep_enabled;
uint64_t insns_flags;
@@ -11468,7 +11467,7 @@ void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb)
ctx.insns_flags = env->insns_flags;
ctx.insns_flags2 = env->insns_flags2;
ctx.access_type = -1;
- ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0;
+ ctx.le_mode = !!(env->hflags & (1 << MSR_LE));
ctx.default_tcg_memop_mask = ctx.le_mode ? MO_LE : MO_BE;
#if defined(TARGET_PPC64)
ctx.sf_mode = msr_is_64bit(env, env->msr);
@@ -11479,25 +11478,25 @@ void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb)
(env->mmu_model & POWERPC_MMU_64B))
ctx.lazy_tlb_flush = true;
- ctx.fpu_enabled = msr_fp;
+ ctx.fpu_enabled = !!msr_fp;
if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
- ctx.spe_enabled = msr_spe;
+ ctx.spe_enabled = !!msr_spe;
else
- ctx.spe_enabled = 0;
+ ctx.spe_enabled = false;
if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
- ctx.altivec_enabled = msr_vr;
+ ctx.altivec_enabled = !!msr_vr;
else
- ctx.altivec_enabled = 0;
+ ctx.altivec_enabled = false;
if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) {
- ctx.vsx_enabled = msr_vsx;
+ ctx.vsx_enabled = !!msr_vsx;
} else {
- ctx.vsx_enabled = 0;
+ ctx.vsx_enabled = false;
}
#if defined(TARGET_PPC64)
if ((env->flags & POWERPC_FLAG_TM) && msr_tm) {
- ctx.tm_enabled = msr_tm;
+ ctx.tm_enabled = !!msr_tm;
} else {
- ctx.tm_enabled = 0;
+ ctx.tm_enabled = false;
}
#endif
if ((env->flags & POWERPC_FLAG_SE) && msr_se)
--
2.1.4
next prev parent reply other threads:[~2016-06-21 21:50 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-06-21 21:48 [Qemu-devel] [PATCH v2 00/10] rework exception model to support the HV mode Cédric Le Goater
2016-06-21 21:48 ` [Qemu-devel] [PATCH v2 01/10] ppc: Fix rfi/rfid/hrfi/... emulation Cédric Le Goater
2016-06-22 2:46 ` David Gibson
2016-06-22 6:48 ` Cédric Le Goater
2016-06-23 5:50 ` David Gibson
2016-06-23 6:08 ` Cédric Le Goater
2016-06-23 6:14 ` David Gibson
2016-07-15 15:17 ` [Qemu-devel] [Qemu-ppc] " Mark Cave-Ayland
2016-09-05 20:25 ` [Qemu-devel] " Thomas Huth
2016-09-05 20:30 ` Cédric Le Goater
2016-09-05 20:51 ` Mark Cave-Ayland
2016-09-06 0:16 ` David Gibson
2016-09-06 7:07 ` Mark Cave-Ayland
2016-09-07 10:50 ` Cédric Le Goater
2016-09-07 11:08 ` Benjamin Herrenschmidt
2016-09-07 12:13 ` Cédric Le Goater
2016-09-07 21:48 ` Benjamin Herrenschmidt
2016-09-08 6:59 ` Cédric Le Goater
2016-06-21 21:48 ` [Qemu-devel] [PATCH v2 02/10] ppc: define a default LPCR value Cédric Le Goater
2016-06-21 21:48 ` [Qemu-devel] [PATCH v2 03/10] ppc: fix exception model for HV mode Cédric Le Goater
2016-06-22 6:27 ` David Gibson
2016-06-21 21:48 ` [Qemu-devel] [PATCH v2 04/10] ppc: Fix POWER7 and POWER8 exception definitions Cédric Le Goater
2016-06-21 21:48 ` [Qemu-devel] [PATCH v2 05/10] ppc: Fix generation if ISI/DSI vs. HV mode Cédric Le Goater
2016-06-21 21:48 ` [Qemu-devel] [PATCH v2 06/10] ppc: Rework generation of priv and inval interrupts Cédric Le Goater
2016-06-22 6:51 ` David Gibson
2016-06-21 21:48 ` [Qemu-devel] [PATCH v2 07/10] ppc: Add real mode CI load/store instructions for P7 and P8 Cédric Le Goater
2016-06-21 21:48 ` Cédric Le Goater [this message]
2016-06-21 21:48 ` [Qemu-devel] [PATCH v2 09/10] ppc: Move exception generation code out of line Cédric Le Goater
2016-06-22 6:57 ` David Gibson
2016-06-21 21:48 ` [Qemu-devel] [PATCH v2 10/10] ppc: Add P7/P8 Power Management instructions Cédric Le Goater
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